I wrote some cross platform VHDL libraries for Xilinx XST, iSim, Altera Quartus II, Mentor Graphics QuestaSim and GHDL. Now I wanted to port my ISE 14.7 project, which uses these libraries to Vivad...

I've been trying to implement a modular exponentiator recently. I'm writing the code in VHDL, but I'm looking for advice of a more algorithmic nature. The main component of the modular exponentiato...

I love the neatness of the ternary operator vs if clauses. Does this operator exist in vhdl? My search was to the contrary. I also checked the when statement out, but it's not an operator, and I w...

What is the difference between type and subtype in VHDL and where should I use them ? My understanding is that subtype is just narrowed down version of one of the primary types, such as integer: ...

ok, what I would like to do is assign a smaller std_vector to a large one, padding out the upper bits with zeros. But, I want something generic and simple that doesn't involve knowing the size of e...

I need to communicate with a chip via a bidirectional databus (ULPI). As far as I can ascertain, data is shifted out on the ULPI bus on rising clock edges, and read on falling clock edges. My prob...

i just wrote a simple VHDL program. I saved the file as a .vhd file. Then I compiled it with ghdl -a test.vhd and then built and executable file with ghdl -e test And finally tried to run i...

I'm not sure I understand the difference between 'downto' vs. 'to' in vhdl. I've seen some online explanations, but I still don't think I understand. Can anyone lay it out for me?

I have some question about Chisel conversion. I know it's theoretical but it would be nice if someone give his opinion. 1) I want to ask why Chisel does not focus on VHDL / SystemVerilog conversio...

I am trying to test a VHDL component, but I can't seem to get this one inout port to give me any behaviour. I've tried setting the port to everything from '1' to '-', but it still comes up as 'U' i...

The standard way to test VHDL code logic is to write a test bench in VHDL and utilize a simulator like ModelSim; which, I have done numerous times. I have heard that instead of writing test ...

Suppose you have a loop for i in 1 downto 0 loop for j in 1 downto 0 loop tS0 <= i; But I need to convert the integer (which is natural) to std_logic. tS0 is declared as std_logic. I am onl...

I'm trying to make a buffer to hold 16, 16-bit wide instructions for a small CPU design. I need a way to load instructions into the buffer from my testbench. So I wanted to use an array of std_lo...

I am new to VHDL. There is a line, given below: constant TIME_DELTA : time := 100 ns; What is this word time in the line? Is it data type just like integer? As I searched VHDL help around inter...

cmd_register: process (rst_n, clk) begin if (rst_n='0') then cmd_r<= (others=>'0'); elsif (clk'event and clk='1') then cmd_r<=...; end if; end process cmd_register; I know "<=" s...

This is the diagram we were given for class: Why wouldn't you just use C4 in this image? If C4 is 1, then the last addition resulted in an overflow, which is what we're wondering. Why do we need...

A lot of VHDL structures has the option for an optional_label before the declaration, but what is this label used for? Here is a process declaration example from vdlande showing the option for a l...

I have the following code (it encodes a number of a pressed button): with buttons select tmp <= "000" when x"1", "001" when x"2", "010" when x"4", "011" when x"8", "100" when others; code...

Is there any free program out there that can parse a collection of VHDL files and build a block diagram from them? I'm looking more for a program that will build a block diagram image to go ...

Anyone knows good environment to program VHDL and simulate it (don't matter Xilinx or Altera) using Linux?

I have looked on the web and the discussions/examples appear to be for traditional software development. Since Verilog and VHDL (used for chip design, e.g. FPGAs and ASICs) are similar to software ...

I am looking at developing on an FPGA, but it would be easier for me to write the code in Python or Scala and have it converted to VHDL or Verilog. I want to have many sensors hooked up to a devic...

I am a newbie to VHDL and can't figure out how to debug VHDL code. Is there any software that could probably give me an insight to the internal signals of my VHDL entity as time passes or somethin...

In VHDL, if you want to increment a std_logic_vector that represents a real number by one, I have come across a few options. 1) Use typecasting datatype conversion functions to change the std_logi...

I am currently trying to use certain legacy VHDL codes into my Verilog design. While it is possible to instantiate VHDL modules within Verilog, I could not find a way to call VHDL functions within ...