Type vs Subtype and down vs to for Integers in VHDL

Question

What is the difference between type and subtype in VHDL and where should I use them ?

My understanding is that subtype is just narrowed down version of one of the primary types, such as integer: subtype small_integer is integer range -128 to 127; All the operations possible on primary type, are also possible on subtypes(of course, with certain limitations) . Also, it is better to use subtypes to prevent errors.

So what is the purpose of the type ?

What is the difference between donwto and to for the integers ? (To get the point across, here is an example)
subtype bit_index is integer range 31 downto 0;
subtype bit_index is integer range 0 to 31;

Thanks !

Executrix

Answer 1

• As you correctly say, a type is the base for subtypes; without type there is no subtype. However, subtypes are only safer in simulation; in real hardware, there are no boundary checks etc...

• The standard libraries of VHDL defines a number of base types for you to build upon, like std_logic, std_ulogic, std_logic_vector (unconstrained, defined in package std_logic_1164) integer, character (defined in package standard), and so on. Your own definitions like std_logic_vector(7 downto 0) create a subtype indirectly (or directly if you define and name your subtypes explicitly)

• When you are looking at your own enumerations, e.g., when describing the states of a state machine, you need a type:

  type tState is (IDLE, DO_SOMETHING, DONE);

• About the downto and to for the integers: it is useless for the integer itself. However, integer, natural etc. can be array index types. In some situations with unconstrained arrays, e.g. like here constant c : std_logic_vector := "1000" the direction of the range of the index type is taken as direction of the literal. In this case, the index type of std_logic_vector is natural, which itself is defined as subtype natural is integer range 0 to integer'high;. Therefor constant c is defined as to and the literal is parsed accordingly ('1' is the LSB)

Terrence

You can also create subtypes of your own unconstrained array types, eg type unconstrained_t is array(natural range <>) of std_logic_vector(1 downto 0); and subtype constrained_t is unconstrained_t(5 downto 0); – Linker

Yes you can, and when you are writing a parser/synthesizer for this it is a real pain in the a*** – Terrence

Answer 2

TO and DOWNTO differs in indianess (MSB at highest bit vs bit 0)

Exploit

the word is "endianness" en.wikipedia.org/wiki/Endianness (i couldn't make an edit of less than 6 characters) – Gibbie

Answer 3

std_logic_vector(7 downto 0) 

"1000 0001" is MSB and "1000 0001" is LSB.

std_logic_vector(0 downto 3) 

"1000 0001" is LSB and "1000 0001" is MSB.

Pernell

The concept of MSB and LSB actually to do with math packages. Since std_logic_vector originally was intended to be only bits, one could argue that there is no LSB and MSB. OTOH, if you go further and look at types unsigned and signed from numeric_std, you will find that consistently the MSB is the left most index of the object. Going further, if you use numeric_std_unsigned, then this principle also gets applied to std_logic_vector. – Salol