verilog Questions
3
Solved
I have a test bench that monitors a bus. Some of the signals (bits) within the bus can be 1'bx. For a variety of reasons, I need to know if any of the signals within the bus are 1'bx. What's the be...
Wendling asked 1/7, 2013 at 20:23
4
Solved
3
Solved
I want to create a 64-bit barrel shifter in verilog (rotate right for now). I want to know if there is a way to do it without writing a 65 part case statement? Is there a way to write some simple c...
Calkins asked 25/9, 2011 at 4:8
3
Solved
If I want to declare a 128 bit vector of all ones, which one of these methods is always correct?
wire [127:0] mywire;
assign mywire = 128'b1;
assign mywire = {128{1'b1}};
assign mywire = 128'hFFF...
Linesman asked 30/9, 2013 at 23:12
5
Solved
What is the difference between:
if (dataoutput[7:0] == 8'bx) begin
and
if (dataoutput[7:0] === 8'bx) begin
After executing dataoutput = 52'bx, the second gives 1, but the first gives 0. Why?...
Rochette asked 8/5, 2011 at 13:7
2
Solved
I am using Yosys to synthesize my Verilog designs. I want to export the FSM in my Verilog design using the Yosys command fsm_export, but it does not generate anything. I wonder how is this command ...
3
Solved
I am confused between these three functions and I was wondering for some explanation. If I set the range how do I make the range exclusive or inclusive? Are the ranges inclusive or exclusive if I d...
7
SystemVerilog added packages to provide namespaces for common code pieces (functions, types, constants, etc). But since packages are not instantiated, they cannot be parameterized, so dealing with ...
Kinnikinnick asked 9/10, 2010 at 0:56
3
Solved
I'm looking for a simple howto to convert a simple Chisel3 module in Verilog.
I take Gcd source code given on official web page of chisel.
import chisel3._
class GCD extends Module {
val io =...
2
I am trying to have verilog mode indent everything using 2 spaces except decls and always. This is what I added to my .emacs:
;; `define are not indented
(setq verilog-indent-level-directive 0)
;...
Suasion asked 22/6, 2015 at 17:29
4
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I'm a bit confused about what is considered an input when you use the wildcard @* in an always block sensitivity list. For instance, in the following example, which signals are interpreted as input...
Chassidychassin asked 11/3, 2012 at 21:27
4
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I have a preprocessor macro that represents a hierarchical path into my design.
Example:
`define HPATH top.chip.block
I need to construct a string which holds the value of `HPATH, so in my exam...
Preemption asked 12/3, 2013 at 22:3
3
Solved
I've encountered in an example for a system verilog code decleration of inputs and outputs for a module without stating their type, e.g logic, wire...
module mat_to_stream (
input [2:0] [2:0] [2:...
Faubion asked 1/4, 2011 at 14:43
3
I Want to Design a Verilog code for Interfacing 16*2 LCD. As in LCD's to give "command" or "data" we have to give LCD's Enable pin a "High to low Pulse " pulse that means
**E=1;
Delay();//Must be...
Ullage asked 7/10, 2013 at 19:7
6
Solved
What does it mean if a task is declared with the automatic keyword in Verilog?
task automatic do_things;
input [31:0] number_of_things;
reg [31:0] tmp_thing;
begin
// ...
end
endtask;
Note:...
Vannavannatta asked 29/8, 2008 at 19:56
12
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I am teaching myself verilog. The book I am following stated in the introduction chapters that to perform division we use the '/' operator or '%' operator. In later chapters it's saying that divisi...
Nisan asked 30/7, 2012 at 16:30
5
I'm looking for a fast way to do a partial sort of 81 numbers - Ideally I'm looking to extract the lowest 16 values (its not necessary for the 16 to be in the absolutely correct order).
The target...
3
Solved
What are the +: and -: Verilog/SystemVerilog operators? When and how do you use them? For example:
logic [15:0] down_vect;
logic [0:15] up_vect;
down_vect[lsb_base_expr +: width_expr]
up_vect [ms...
Cadmar asked 22/7, 2013 at 0:36
4
Solved
For instance, say I have a reg [7:0] myReg
I assign it the value -8'D69
I know Verilog stores it as 2's complement so it should be stored as
10111011
The question I have now is if I were to per...
Miki asked 13/9, 2012 at 5:33
8
I'm using a GUI simulator, and they both seem to do the same thing.
Thenceforward asked 7/3, 2010 at 4:0
6
I want to design a synthesizable module in Verilog which will take only one cycle in calculating square root of given input of 32 bit.
2
I am required to simulate Verilog programs as part of my syllabus. But, my college uses Xilinx ISE, and it isn't available for Mac.
So please help me out with the best software and also some detai...
1
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I am designing a 16 bit ALU in verilog based on an existing RISC ISA. The ISA says that the carry flag is set when the operation is unsigned, and overflow is set when the operation is signed. The i...
Jackqueline asked 9/9, 2021 at 21:23
5
Solved
Is it possible to write a function that can detect the input data width automatically? For example, consider the parity function below:
function parity;
input [31:0] data;
parity = ^ data;
endf...
Salsify asked 27/3, 2014 at 19:2
2
Solved
I want to create this generic wrapper for a bunch of modules I am writing. The wrapper should provide the ability to connect these modules to different type of NoCs without having to change the beh...
Battik asked 10/4, 2015 at 20:57
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