vhdl - 3 - McMap

2

Solved

Difference between mod and rem operators in VHDL?

I came across these statements in VHDL programming and could not understand the difference between the two operators mod and rem 9 mod 5 (-9) mod 5 9 mod (-5) 9 rem 5 (-9) rem 5 9 rem (-5) ...

vhdl

Janeanjaneczka asked 15/9, 2014 at 13:9

1

Solved

VHDL initialize generic array of std_logic_vector

I would like to implement a ring buffer for convolution stuff in VHDL and make it generic. My problem is how to initialize the internal data without introducing further signals or variables. Usual...

arrays generics initialization vhdl

Honorific asked 22/11, 2017 at 13:39

4

Solved

How do I make Quartus II compile faster

I'm using Altera Quartus 2 to do a custom 8 bit processor and it takes forever to compile on my laptop. I'm only using simulations and making my processor in schematic (block diagram) and VHDL. Rig...

vhdl quartus

Possessed asked 10/12, 2008 at 2:46

2

Solved

VHDL arithmetic shift_left

With the shift_left function of ieee.numeric_std, I want to shift a signal to left and insert 1 or 0 from the right. signal qo: signed (3 downto 0) := (others=>'0'); qo <= shift_left(qo,1); ...

vhdl

Partial asked 10/10, 2017 at 12:22

6

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shift a std_logic_vector of n bit to right or left

I have a vector signal tmp : std_logic_vector(15 downto 0) I have to shift it to left or right of n bit. how can I realize this operation. I thought to concatenation operation but I didn't know ho...

vhdl

Warnerwarning asked 26/1, 2012 at 12:27

2

Solved

When to use VHDL library std_logic_unsigned and numeric_std?

I use VHDL-200X in ISE.I always use data type like std_logic_vector,std_logic,integer,boolean and real.Always use std_logic_vector convert to integer and reverse. My team mates ask me to use these ...

vhdl fpga

Spatter asked 16/8, 2017 at 2:19

4

Solved

VHDL: creating a very slow clock pulse based on a very fast clock

(I'd post this in EE but it seems there are far more VHDL questions here...) Background: I'm using the Xilinx Spartan-6LX9 FPGA with the Xilinx ISE 14.4 (webpack). I stumbled upon the dreaded "Ph...

vhdl clock fpga

Maus asked 6/3, 2013 at 10:37

6

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Should you remove all warnings in your Verilog or VHDL design? Why or why not?

In (regular) software I have worked at companies where the gcc option -Wall is used to show all warnings. Then they need to be dealt with. With non-trivial FPGA/ASIC design in Verilog or VHDL there...

verilog vhdl system-verilog fpga asic

Romanaromanas asked 27/4, 2010 at 15:1

1

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Difference between unsigned and std_logic_vector

can anyone tell me about the difference between below written statement. signal A: **unsigned**(3 downto 0); signal B: **std_logic_vector**(3 downto 0);

vhdl fpga

Pyrene asked 15/6, 2017 at 4:43

1

Solved

Large Array Initialization to 0

Is there a way to initialize a two dimensional array without giving all the values one by one. I have signal declaration like : type t_id_data is array (integer range <> ) of integer; ty...

vhdl

Filler asked 1/6, 2017 at 13:2

5

Solved

VHDL Variable Vs. Signal

I have been reading a text (Don't have it in front so can't give the title) about VHDL programming. One problem I've been having a hard time understanding from the text is when to use a variable vs...

vhdl

Velleman asked 18/3, 2013 at 19:58

2

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Delta Cycles and Waveforms

Can anyone explain how delta cycles affect waveforms simulated by VHDL? I understand that it has to do with how VHDL determines precedence but I'm not exactly sure how.

vhdl

Runny asked 27/4, 2017 at 8:32

2

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VHDL - Function/Procedure for any type of array

Question: How does one declare, if possible, a function intended for a parameter of any type T where the only constraint on T is that it was defined as a 1D array as in type T is array ( integer ...

vhdl

Interdigitate asked 10/4, 2017 at 13:44

2

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Synthesizable multidimensional arrays in VHDL

I need to use multidimensional arrays to represent matrices in my design. I have tried the two available options: Declaring array of arrays type t11 is array (0 to c1_r2) of std_logic_vector(3...

arrays multidimensional-array vhdl

Intermingle asked 4/6, 2015 at 18:18

3

Solved

How can I read binary data in VHDL/modelsim whithout using special binary formats

I am writing a VHDL test bench for a ethernet MAC. The testbench consists of a package and an combined entity + architecture file. I want to read the ethernet frames that the testbench will send to...

io vhdl modelsim

Yulan asked 5/1, 2013 at 16:14

5

VHDL: use the length of an integer generic to determine number of select lines

I'm trying to create a reusable barrel shifter; it takes an input array of bits and shifts them a certain number of positions (determined by another input). I want to parameterize the module so tha...

generics vhdl

Feu asked 5/10, 2012 at 16:4

2

Solved

Convert enum type to std_logic_vector VHDL

I want to know if it is possible to convert a enum type, like FSM states to std_logic_vector or integer. I'm doing a testbench with OSVVM for a FSM and I want to use the scoreboard package to autom...

vhdl

Usher asked 15/2, 2017 at 16:30

6

Solved

Reverse bit order on VHDL

I'm having trouble doing something like b(0 to 7) <= a(7 downto 0) when I compile it with ghdl, I have an order error. The only way I have found to make my circuit work is the following: lib...

vhdl

Usage asked 27/11, 2012 at 12:31

2

Solved

How to pre-process source files while a Sphinx run?

I have set up a Sphinx documentation for my project and would like to extract doc strings for the source files and embed them into the final documentation. Unfortunately, the source file's language...

python python-3.x vhdl python-sphinx read-the-docs

Rear asked 24/5, 2016 at 17:50

3

How to specify an integer array as generic in VHDL?

I am trying to create a generic driver for an SPI based IO expander. The idea is to pass initialization values in the instantiation, that matches the requested IO setup. My current attempt look li...

generics instantiation vhdl

Sakhuja asked 3/8, 2012 at 7:49

2

Solved

Generic in verilog from a vhdl programmer

What's the equivalent of the generic in verilog? For example entity my_entity generic(a : integer); port(x : in std_logic; y out std_logic); end entity my_entity; What's the equivalent for gener...

syntax vhdl verilog

Beslobber asked 27/7, 2016 at 20:51

1

Solved

"component instance "uut" is not bound" when simulating test bench with GHDL simulator

I am having a problem with using GHDL (http://ghdl.readthedocs.io/en/latest/) to simulate my VHDL design. So, when I use the command ghdl -e Averager_tb to compile the test bench with GHDL I get th...

vhdl fpga hdl ghdl

Zelda asked 21/7, 2016 at 11:18

2

Solved

Why should an HDL simulation (from source code) have access to the simulator's API?

This is a question inspired by this question and answer pair: call questa sim commands from SystemVerilog test bench The questions asks how Verilog code could control the executing simulator (Ques...

vhdl verilog simulation questasim

Baroscope asked 20/6, 2016 at 22:55

4

Solved

VHDL - How should I create a clock in a testbench?

How should I create a clock in a testbench? I already have found one answer, however others on stack overflow have suggested that there are alternative or better ways of achieving this: LIBRARY ie...

simulation vhdl clock hardware

Septicidal asked 28/7, 2013 at 2:47

6

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What is the purpose of the `std_logic` enumerated type in VHDL?

What is the purpose of the std_logic enumerated type? 'U': uninitialized. This signal hasn't been set yet. 'X': unknown. Impossible to determine this value/result. '0': logic 0 '1': logic 1 'Z': H...

vhdl digital

Monophony asked 20/9, 2012 at 1:6

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