Declaring an array within an entity in VHDL

Question

I'm trying to make a buffer to hold 16, 16-bit wide instructions for a small CPU design.

I need a way to load instructions into the buffer from my testbench. So I wanted to use an array of std_logic_vectors to accomplish this. However, I am getting a syntax error and I'm not sure why (or if I'm allowed to do this in VHDL for that matter).

The syntax error is at the line where I declare instructions

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;




entity instruction_buffer is
    port
    (
    reset               : in std_logic;
    instructions        : in array(0 to 15) of std_logic_vector(15 downto 0);
    instruction_address : in  std_logic_vector(3 downto  0);
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;

I've tried doing like this as well, but then I get syntax errors in my entity port mapping telling me that std_logic_vector is an unknown type. I swear, VHDL's syntax errors are less meaningful than C haha

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

package instructionBuffer is
    type instructionBuffer is array(0 to 15) of std_logic_vector (15 downto 0);
end package instructionBuffer;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(3 downto  0);
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;

Devonadevondra

Answer 1

There is no need to split into two files, simply put all code into one file. You can also use generics inside your package for scalability:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package instruction_buffer_type is
constant INSTRUCTION_BUFFER_ADDRESS : integer := 4;  --bits wide
constant INSTRUCTION_BUFFER_DATA    : integer := 16; --bits wide
type instructionBuffer is array(0 to 2**INSTRUCTION_BUFFER_ADDRESS -1) of std_logic_vector (INSTRUCTION_BUFFER_DATA -1 downto 0);
end package instruction_buffer_type;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.instruction_buffer_type.all;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(INSTRUCTION_BUFFER_ADDRESS-1 downto  0);
    instructions        : in instructionBuffer;
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(INSTRUCTION_BUFFER_DATA-1 downto 0)
    );
end instruction_buffer;

Nobody

Answer 2

I got it working:

In one file I have the following:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

package instruction_buffer_type is
    type instructionBuffer is array(0 to 15) of std_logic_vector (15 downto 0);
end package instruction_buffer_type;

and then in another I have:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

use work.instruction_buffer_type.all;

entity instruction_buffer is
    port
    (
    instruction_address : in  std_logic_vector(3 downto  0);
    instructions        : in instructionBuffer;
    clk                 : in std_logic;
    instruction_out     : out std_logic_vector(15 downto 0)
    );
end instruction_buffer;

It's so obvious that this language was a government project. It's so overly redundant.

Devonadevondra

It's not redundant, it's because packages and entitys are different compilation units. See here: https://mcmap.net/q/1324574/-vhdl-can-you-declare-a-package-and-an-entity-in-the-same-file. You can still keep it all in one file, just make sure you have the right library clauses in for each unit. – Calipash

Answer 3

multidimensional array

package aray is
constant aM: integer :=3;
constant vM:    integer :=3;
type argay is array (1 to aM) of std_logic_vector (vM downto 0);
type arrgay is array (1 to aM) of argay;
end package aray;

Amazed

create bdf and export to vhdl – Amazed