Testing VHDL / FPGA Using Python and A Simulator [closed]

Question

The standard way to test VHDL code logic is to write a test bench in VHDL and utilize a simulator like ModelSim; which, I have done numerous times.

I have heard that instead of writing test benches in VHDL, engineers are now using Python to test there VHDL code.

Questions:

1. How is this done?

   • Is this done by writing a test bench in Python and then compiling this Python file or linking into Modelsim?
   • Is this done in Python using a module like myHDL and then linking/importing your VHDL file into Python? Is so, how is the timing diagram generated?

2. When writing a test bench in Python can you use standard Python coding/modules or just a module like myHDL?

   • For example if I want to test a TCP/IP stack in VHDL, can I use the socket module in Python to do this (i.e. import socket)?

3. Is there a reference, paper, or tutorial that shows how to do this? I've checked the Xilinx, Altera, and Modelsim websites but could not find anything.

The only thing I find online about using Python for FPGA are a few packages: with myHDL being the most referenced.

Alabama

See also: cocotb.readthedocs.org/en/latest/introduction.html – Xuthus

Look at Chris Higgs answer to Can you interface a Modelsim testbench with an external stimuli, where in the link to Tutorial: Ping. – Winger

You can try out Cocotb on EDA Playground : www.edaplayground.com . – Gahan

Possible duplicate of Python in verification test of VHDL design – Queenie

One example of a Python test suite that can drive a Modelsim process. – Nucleolated

cocotb needs VHPI, which AFAIK is only available for ModelSim DE, which is the most expensive version. Maybe it's worth trying ghdl – Lorient

Answer 1

Why Python is good for this

Python is an efficient language for writing reference models in or to process and verify output files of your testbench. Many things take much less time to program in Python than in a VHDL testbench.

One key feature of Python that makes it so suitable is the automatic usage of big integers. If your VHDL uses >64 bit widths, it can be tedious to interface with that in other languages. Also when verifying arithmetic functionality, e.g. Python's Decimal package is a convenient tool to build high-precision references.

How can this be done?

This is an example that does not rely on any other software tools.

A straightforward practical way to interface Python is via input and output files. You can read and write files in your VHDL testbench as it is running in your simulator. Usually each line in the file represents a transaction.

Depending on your needs, you can either have the VHDL testbench compare your design outputs to a reference, or read the output file read back into a Python program. If using files takes too long, at least in Linux it's easy to set up a pipe with mkfifo that you can use as if it were a file, and you can then have your Python program and simulator read from and write to in sync.

Using standard Python modules

With the method I described, you'll have to find a way to separate whatever that module is doing into a stream of data or raw transactions. Unfortunately for your example of a TCP/IP stack, I see no straightforward way to do this and it would probably require significant clarification to discuss further.

More information

Several useful things are linked to in the comments above, especially the link posted by user1155120: https://electronics.stackexchange.com/questions/106784/can-you-interface-a-modelsim-testbench-with-an-external-stimuli

Aphelion

Answer 2

Maybe it is better to design whole design in some other language like SystemC/myHdl/HWToolkit test it and then only export it to your target language.

In order to simulate HDL and drive it from regular python code you have to use framework like cocotb/PyCoRAM and others. Still it gets complicated really fast.

One of the best approaches I have found is to use simulator + agents with queues/abstract memory and in code work only with this queues and not simulator or model itself. It makes writing of testbenches/verification simple. In python-hw word only HWToolkit currently uses this approach: tx_rx_test.py

Zamarripa

Answer 3

You could write IO from python to text files and use your traditional File-IO VHDL methods to stimulate the DUT.

But, you are better off performing verification in a native environment using a language that was developed to perform functional verification. Using Systemverilog and the Modelsim superset packaged as "Questa Prime" (if you have access to it) is much better.

Assuming you want your python file(s) to be a part of your real-time simulation in terms of transfer functions and/or stimulus generation, they will need to be converted to shared-object files. everything else is post-processing, and is not simulator dependent. e.g. writing output files for later comparison. Non-native simulations, using shared object files, require access via VPI/VLI/FLI/PLI/DPI (depending on what language/tool you are using) which then introduces the overhead of passing the kernel back and forth across the interface. i.e. stop sim, work external, run sim, stop sim, etc.

Systemverilog (IEEE-1800) was developed for IC designers, by IC designers to address the issue of functional verification. while I am all for re-use in terms of .so files from system engineering simulations, if you are writing the testbench (which you shouldn't write your own TB, but that is another discussion), you would be better off using SV given all the built-in functions for constraining stimulus generation, functional coverage and reporting via UCDB.

you should have a reference manual in your Modelsim install to describe using the Programming Interface. you can learn more here : https://verificationacademy.com/ but, it is highly SV-centric... Unfortunately, VHDL is not a verification language, even with the additions they have made to be more like SV, it is, still, better categorized as a modeling language.

Gona

Answer 4

Check out PyVHDL. It integrates Python and VHDL with an Eclipse GUI with editing, simulation and VCD generation & display.

GUI Image: https://i.sstatic.net/BvQWN.jpg

Object

Generally, links to a tool or library should be accompanied by usage notes, a specific explanation of how the linked resource is applicable to the problem, and some sample code. If the tool or library is not free-to-use, please also mention this in your answer. – Om