I'm using a PowerShell script to control different compilation steps of an compiler (ghdl.exe). The compiler has 3 different output formats: No output and no error => $LastExitCode = 0 outputs o...

i just wrote a simple VHDL program. I saved the file as a .vhd file. Then I compiled it with ghdl -a test.vhd and then built and executable file with ghdl -e test And finally tried to run i...

I am having a problem with using GHDL (http://ghdl.readthedocs.io/en/latest/) to simulate my VHDL design. So, when I use the command ghdl -e Averager_tb to compile the test bench with GHDL I get th...

I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(m...

Whenever I create a VHDL design I tend to have many modules. Each of these modules are then connected to one main file and so everything is synthesised. But I want to write seperate test benches fo...