convert integer to std_logic
Asked Answered
L

5

8

Suppose you have a loop

for i in 1 downto 0 loop
    for j in 1 downto 0 loop
        tS0 <= i;

But I need to convert the integer (which is natural) to std_logic. tS0 is declared as std_logic. I am only doing it one bit (0 or 1). That is, my i and j can only represent the value {0,1}.

I think I am heading to the wrong approach here. Can someone please tell me what should I do instead?

I don't think std_logic has to_unsigned method. i tried letting tS0 to be a vector (1 down to 0), and assigned like tS0(0) <= i, and etc. But it still didn't work out.

Thank you very much!

Latinalatinate answered 3/9, 2011 at 0:6 Comment(1)
electronics.stackexchange.com/questions/4482/…Whisker
S
6

You will need to use a vector, either unsigned or std_logic, but it can be one bit long. ie:

signal tS0 : unsigned (0 downto 0);
...
tS0 <= to_unsigned(i, tS0'length);

...or...

signal tS0: std_logic_vector(0 downto 0);
...
tS0 <= std_logic_vector(to_unsigned(i,tS0'length);
Scraggy answered 3/9, 2011 at 4:14 Comment(0)
F
14

There is no need to convert from integers. You can just iterate over the std_logic datatype:

for i in std_logic range '0' to '1' loop
   ts0 <= i;
end loop;
Fathomless answered 5/9, 2011 at 13:58 Comment(1)
Nice one! Thank you!!Gigantism
A
7

I'd write a function:

function to_std_logic(i : in integer) return std_logic is
begin
    if i = 0 then
        return '0';
    end if;
    return '1';
end function;

then use:

ts0 <= to_std_logic(i);
Athanasian answered 5/9, 2011 at 10:55 Comment(1)
For me, this is a much more useful and accurate answer than the accepted one.Surfacetoair
S
6

You will need to use a vector, either unsigned or std_logic, but it can be one bit long. ie:

signal tS0 : unsigned (0 downto 0);
...
tS0 <= to_unsigned(i, tS0'length);

...or...

signal tS0: std_logic_vector(0 downto 0);
...
tS0 <= std_logic_vector(to_unsigned(i,tS0'length);
Scraggy answered 3/9, 2011 at 4:14 Comment(0)
L
5

You can do it like this. It looks a little simplier.

ts0 <= std_logic(to_unsigned(i, 1)(0));

You will build a unsigned vector by using the to_unsigned function. Then you grap the lowest bit and convert it to std_logic and then you assign it to the signal.

This is how it works fine :-).

Leiker answered 27/11, 2013 at 7:24 Comment(0)
A
1

Improving on a previous answer, you could write:

ts0 <= to_unsigned(i, 1)(0);

Provided you include the "numeric_std" library, in which that function is defined:

library IEEE;
use IEEE.numeric_std.all;

You can skip the explicit cast to "std_logic" type because the return type of "to_unsigned()" is an array of "std_logic" itself:

type UNSIGNED is array (NATURAL range <>) of STD_LOGIC;
Amputate answered 19/11, 2018 at 9:13 Comment(0)

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