Debugging VHDL: How to?

Question

I am a newbie to VHDL and can't figure out how to debug VHDL code.

Is there any software that could probably give me an insight to the internal signals of my VHDL entity as time passes or something like that?

Please help.

Ichthyosaur

there is no constraint as to the operating system , i have access to both Windows and Linux – Ichthyosaur

Answer 1

As the other posts have pointed out, you'll likely need a simulator like GHDL. However, to debug your simulation, there are a few different methodologies:

• Classic print statements -- just mix in writeline(output,[...]) in your procedural code. See this hello world example. If you're just getting started, then adding print statements will be invaluable. For most of the simulation debug that I do ( and that is part of my job ), I do almost all of the debug based on print statements that we've built up in our design and testbench. It is only for the final debug, or for more difficult issues that I use the next debug method.

• "Dumping" the simulation ( for GHDL see this page and this one ). This is a cycle by cycle trace of your design ( or a subset of your design). It's as if you hook up a logic analyzer to every single wire in your design. All the info you could ever want about your design, but at a very low level -- the signal level. To use this methodology:

  1. Create a simulation "dump". The base format for such a dump is a Value Change Dump or VCD. Whichever simulator you use, you'll need to read the documentation on how to create a VCD. ( You can also search "dump" in your docs -- your simulator may use a different file format for its dumps.)

  2. Once you create a simulation dump, you then load your dump into a wave-form viewer. If you're using the gEDA package, then you would use gtkwave to view the dump.

note If you want to use GHDL and gtkwave to debug your VHDL code, you can install them on ubuntu with command:

% sudo apt-get install geda ghdl

( assuming you have root access to the machine running ubuntu)

Thermochemistry

your answer is very informative. I will try it out asap and ask for further assistance if necessary – Ichthyosaur

Answer 2

Xilinx offers free version of its design suite: http://www.xilinx.com/tools/webpack.htm. Webpack contains VHDL simulator, although last time I tried I've liked ModelSim's simulator better. It might have changed though.

Wepack is also different from ModelSim as it's not only simulator but full-fledged FPGA design suite.

ModelSim's disadvantage is its license -- as far as I'm concerned it's free for students only.

Almaraz

Answer 3

The others mentioned here are likely more appropriate based on cost and availability. However the best HDL/netlist debugger I've used by far is Verdi.

Solidus

Answer 4

What you are looking for is an VHDL simulator. There are several alternatives to choose from:

1. Mentors Modelsim
2. Xilinx ISim
3. Aldec Riviera and ActiveHDL
4. Simili

The Simili software is available as a free version with limited performance.

Once you have the simulator installed you need to learn how to use it. Generally you will have to write a testbench in VHDL too, but some of the simulators will let you create the stimuli signals from a graphical user interface. You can find a large number of examples of VHDL-based testbenches on this page: VHDL Tutorials.

In the simulator you are able to visually inspect the state of your design in the waveform viewer and also be able to set breakpoints in your code to debug the design.

Nalley

Answer 5

Use a simulation software like ModelSim. This kind of software is usually quite expensive. In general if with your vhdl synthethizer you'll get some lightweight variant of it or similar software which is enough for smaller things.

Gorki

Not expensive: A lightweight version of ModelSim comes for free with Altera's Quartus. – Underexposure

Answer 6

For small jobs which don't push the language spec all the way, GHDL works fine as a simulator IME. As you push things further (and you must, you can't debug any sizeable piece of code just in silicon) you may find you need to spend some money on something like Mentor's Modelsim/Questa or Aldec's ActiveHDL/Riviera.

Gunilla

Answer 7

first i created test bench to test my component, used isim to simulate this test bench, i inserted break points in the main code areas, used the step into button to step into code, or the run button to jump to next break point same as i am used to do with any programming language

Basically

Answer 8

The professional way to “Debug” VHDL is to create a “testbench”. Like everything else VHDL it’s complicated. Here’s a “how to testbench” link: vhdl Testbenches

I am very lazy. I am also not professional. I prefer to do what is known as “forcing”. If you are using Xilinx, ModelSim, or Vivado, then you have the ability to toss your VHDL code into a “simulation”. There you can add signals to a waveform, select those signals (right click on them) and force their values to be ‘0’ or ‘1’. Then after “forcing” your input, run the simulation for a few nanoseconds and look at the output.

Soughtafter