Program for drawing VHDL block diagrams? [closed]

Question

Is there any free program out there that can parse a collection of VHDL files and build a block diagram from them?

I'm looking more for a program that will build a block diagram image to go along with the documentation for the hierarchy, similar to the way javadoc builds a class diagram after parsing the documentation for a series of classes.

Kaz

Answer 1

There's nothing open-sourced anyways. A while back, I looked for something simliar for verilog designs with no success.

Tenno

Answer 2

Altera's Quartus can compile VHDL and provide you with the top-level schematic blocks, representing the VHDL signals. Ditto with Xilinx ISE. Its not open source software, but it is free to download and use.

Belfort

Just curious, but you wouldn't happen to know where this is in ISE would you? – Mashe

In Xilinx ISE: When in "Implementation mode" (selectable from combo-box above hierarchy tree), one of subtasks of Synthesis process is "View RTL Schematics". However, this does not show the original structure of VHDL entities, it shows synthesis result in form of schematics. It means some entities are replaced/implemented with recognized FPGA cells, and as such it isn't usable for documentation. – Jeu

Answer 3

Synplify Pro and Synplify Premier has an RTL viewer and is my preferred program of the ones I have seen. I have also seen RTL viewers in Xilinx ISE, Altera's Quartus and Mentor's HDL designer.

Darya

Answer 4

Mentor's HDL designer is for this purpose, but it's not free, although you can probably get a discounted student version.

As thetrus noted Quartus has an RTL viewer as well, but the quality of diagrams produced by it is pretty poor - you can't really use them for documentation. They're most useful for catching synthesis bugs.

Linctus

Answer 5

HDL Works in Ede Netherlands has EASE which is similar to Mentor's HDL Designer but much more nimble and far less expensive, I have used both. Of the two, EASE is far easier to get going with and maintain from my experience. I found the Mentor tool hard to use and unstable but I assume it has since been improved. EASE is much more intuitive and the focus is still on the code and less on tool use. Unlike the post-synthesis tools from Xilinx, Synopsys and others, the HDL Works tool and the Mentor HDL Designer are pre-synthesis. A tool that is somewhat in-between pre and post is Sigasi. I have seen but as yet have not used the latter. It looks promising. Links: https://www.hdlworks.com/products/ease/index.html

http://www.sigasi.com/

Aboutface

This 9! year old question was closed for a good reason. The OP is asking about a free tool, and people start pushing commercial products. In the mean time the question is not even relevant anymore as FPGA vendors include these tools in their design software: for example Xilinx IP-integrator. – Vanmeter