Converting Chisel to Vhdl and SystemC?

Question

I have some question about Chisel conversion. I know it's theoretical but it would be nice if someone give his opinion.

1) I want to ask why Chisel does not focus on VHDL / SystemVerilog conversion. Although both Verilog and VHDL are same, in some countries especially Europe prefer VHDL. 2) Similarly, C++ model is used for simulation models. Why Not SystemC for this purpose?

I was reading some notes and find out FIRRTL is the middleman for converting CHISEL-->FIRRTL--> Verilog and CHISEL---> FIRRTL--> C++ model.

Is it a nice idea to use the (Low)FIRRTL specs to Convert the VHDL and SystemC models.?

Vereeniging

You can try SpinalHDL. It is also Scala-based, has the same concept and compiles to VHDL. – Turd

Also, I'm working on a new type of Hardware Description Language, DFiant. It will compile to VHDL. You can read about it here. – Turd

@Oron Port Thanks for the suggestion. I have seen the SpinalHDL which similar with Chisel very much. But I am thinking of one common platform. – Vereeniging

Answer 1

The short answer is that supporting VHDL and SystemC backends simply hasn't been a priority for the developers.

There are a few reasons why it hasn't been a priority:

1. People rarely ask for it. This is the first time I've seen this come up since this issue on the Chisel 2 repo back in 2014.
2. Lack of developer time. We have quite a backlog of features already so additional backends simply haven't been a priority. While I think the implementation effort of adding a VHDL and/or SystemC backend isn't too bad, they would also present an additional maintenance and verification overhead. All this being said, Chisel3 and FIRRTL are open-source projects so we welcome contributors who want to help us with particular features!
3. Unclear benefits. VHDL (at least) is interoperable with Verilog so it's unclear why a VHDL backend is needed. As far as tooling, my understanding is that Verilog seems to have equivalent or better support than VHDL. For readability/debug-ability concerns, the generated code is not really intended for reading anyway; rather, most users use waveforms and only use the emitted code for the source-locators pointing back to the Scala source. I'm less familiar with SystemC so there might be some nice benefits of emitting it that I'm unaware of!

I'm most certainly unaware many benefits so please let me know what I'm missing!

Dumah

For your point 3) insights.sigasi.com/opinion/jan/verilogs-major-flaw.html Verilog can actually be very non-deterministic. VHDL on the other hand is not. Having personally run into non-deterministic Verilog simulations, I can tell you I prefer VHDL any day. – Grussing

I should clarify that I am not arguing for writing Verilog. I would argue people should write Chisel :). As a target for emitted code; however, we can simply not emit Verilog that exhibits such problems. – Dumah

Answer 2

One other bit that might help future readers: as jkoenig mentioned, the purpose of Chisel isn't to generate HDL code for humans to use. The purpose is to create a new language for designing hardware.

Verilog just happens to be a language that is spoken by lots of hardware tools, so generating Verilog is an easy way to make Chisel interoperable with the current ecosystem of CAD tools. Otherwise you would have to write your own synthesis and place-and-route tools if you actually wanted to implement Chisel designs on real hardware. In this respect, Verilog or VHDL is a moot argument. Either one would work, and as long as one works, the other is not really necessary.

Icebreaker

I didn't see this until just now, but this is a great response. Thanks! – Dumah

But if Chisel also generated VHDL you would cover EDA tools that only use VHDL as input. – Subulate

@BjörnLindqvist All the tools I've ever used support both VHDL and Verilog... are there major tools/vendors that only support VHDL? – Icebreaker