VHDL: with-select for multiple values

Question

I have the following code (it encodes a number of a pressed button):

with buttons select
  tmp <= "000" when x"1",
         "001" when x"2",
         "010" when x"4",  
         "011" when x"8",
         "100" when others;
code <= input(1 downto 0);
error <= input(2);

I am trying to rewrite it without using tmp signal. Is it possible? The following doesn't work:

with buttons select
  error & code <= "000" when x"1",
                  "001" when x"2",
                  "010" when x"4",  
                  "011" when x"8",
                  "100" when others;

Mosesmosey

Answer 1

Instead of with select, you could use case:

my_process_name : process(buttons)
begin
  case buttons is
    when x"1" =>
      error <= '0';
      code  <= "00";
    when x"2" =>
      error <= '0';
      code  <= "01";
    when x"4" =>
      error <= '0';
      code  <= "10";
    when x"8" =>
      error <= '0';
      code  <= "11";
    when others =>
      error <= '1';
      code  <= "00";
  end case;
end process;

Osteal

It only works in processes: quicknet.se/hdc/hdl/educaton/mux4_1/index.htm – Mosesmosey

Is there a particular reason you don't want to place it in a process? – Osteal

I'm simply learning VHDL and I was looking for simplest, most elegant solution. Is there any semantic difference if I put combinatorial code in a process? – Mosesmosey

Edited to show combinatorial within a process. Typically within the parenthesis of the process(), you'll add signal to the sensitivity list, i.e. inputs of your combinatorial logic or if sequential your clock and reset. The sensitivity list isn't typically needed for synthesis but for simulations tells the simulator to only look at this process if the signals within the sensitivity list changes. If you just have it within the architecture I believe the simulator evaluates that line every tick. – Osteal

Answer 2

Or you could just write this as 2 separate with/when statements:

with buttons select
  error <= '0' when x"1",
           '0' when x"2",
           '0' when x"4",  
           '0' when x"8",
           '1' when others;
with buttons select
  code <= "00" when x"1",
          "01" when x"2",
          "10" when x"4",  
          "11" when x"8",
          "00" when others;

or alternatively:

error <= '0' when (buttons = X"1" or buttons = X"2" buttons = X"4" buttons = X"8") else '1'; 
code <= "00" when buttons = X"1" else "01" when buttons = X"2" else "10" when buttons = X"4" else "11" when buttons = X"8" else "00"; 

VHDL is a compiled language - or synthesised. Any format is OK as long as the synthesis tool creates the relevant logic construct. The rest is symantics to allow code to be understood and maintained.

Wouldbe