vhdl - McMap

3

Solved

VHDL-2008 to_01 conversion

I am getting some unexpected behavior when using the to_01 conversion function in VHDL-2008. My expectation would be that vector bits that can clearly be interpreted as high or low are mapped to '1...

vhdl

Raphaelraphaela asked 22/11, 2017 at 9:10

4

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How do I install GTKWave on Windows?

I am desperately trying to install GTKWave on my Windows machine. Can anyone give me so tips or redirect me to a good tutorial (or even better, post a small tutorial here)? I think the documentati...

gtk verilog vhdl simulator gtkwave

Haile asked 22/6, 2013 at 19:4

3

What does 1-, 2-, or 3-process mean for an FSM in VHDL?

It seems like there is quite some debate about how to code finite state machines (FSMs) in VHDL. People talk about 1-process, 2-process, or 3-process FSMs as if everyone knew exactly what it means ...

coding-style vhdl fsm

Kernite asked 28/10, 2014 at 21:23

5

Fast, small area and low latency partial sorting algorithm

I'm looking for a fast way to do a partial sort of 81 numbers - Ideally I'm looking to extract the lowest 16 values (its not necessary for the 16 to be in the absolutely correct order). The target...

algorithm sorting vhdl verilog fpga

Vanwinkle asked 9/11, 2012 at 10:28

8

Solved

Error in VHDL (Xilinx): failed to link the design

why I get error in VHDL for this? Also, sometimes: cannot do process as a process failed previously? Many thanks.

vhdl xilinx

Tameratamerlane asked 12/4, 2014 at 16:45

3

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How to use 3-input logic gates in vhdl?

I am just learning vhdl, and am trying to use a 3-input nand gate. The code I have is: G => (A nand B nand C) after 3 ns; but this does not compile.

vhdl

Prediction asked 2/11, 2011 at 16:48

5

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Altera Quartus Error (12007): Top-level design entity "alt_ex_1" is undefined

I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution. I'm new to VHDL and am trying to compile the si...

vhdl intel-fpga quartus

Atom asked 14/9, 2014 at 10:31

5

Error adding std_logic_vectors

I wanna have a simple module that adds two std_logic_vectors. However, when using the code below with the + operator it does not synthesize. library IEEE; use IEEE.std_logic_1164.all; use IEEE.s...

vhdl fpga

Sharpie asked 28/10, 2010 at 12:20

5

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What is the difference between "wait until rising_edge(clk)" vs "if rising_edge(clk)"?

I came across two styles of process statements in VHDL. process(clk) begin if rising_edge(clk) ...do something... The other one is process begin wait until rising_edge(clk) ...do something... ...

vhdl

Misbecome asked 22/9, 2015 at 12:35

2

Solved

Using hex values in constants

I am trying to create a few constants and assign hex numbers to them; however, I keep getting errors. I want the constant FOO_CONST to be equal to 0x38 Like this... constant FOO_CONST : integer := ...

hex vhdl constants

Jumbled asked 4/8, 2016 at 21:41

3

Solved

What' s the difference between <= and := in VHDL

Currently, I am learning some FPGA design techniques using VHDL, my problem is whether we can use := and <= interchangeably in VHDL or not, though I've seen the use of := in constants declaratio...

embedded logic vhdl colon-equals

Ina asked 13/8, 2012 at 1:7

4

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VHDL: Is there a convenient way to assign ascii values to std_logic_vector?

In verilog, I can assign a string to a vector like: wire [39:0] hello; assign hello = "hello"; In VHDL, I'm having difficulty finding a method like this: SIGNAL hello : OUT std_logic_vector (...

ascii vhdl verilog

Worried asked 6/4, 2014 at 22:43

4

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Way to initialize synthesizable 2D array with constant values in Verilog

in VHDL, I can easily do this: constant cmdbytes : bytearray(0 to Total) := (x"05", x"00", x...}; I want synthesizable constants so that when the FPGA starts, this array has the data I supplied....

arrays initialization constants vhdl verilog

Eloiseloisa asked 2/1, 2013 at 22:22

3

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Verilog question mark (?) operator

I'm trying to translate a Verilog program into VHDL and have stumbled across a statement where a question mark (?) operator is used in the Verilog program. The following is the Verilog code; 1 mo...

operators vhdl verilog

Streetwalker asked 9/9, 2012 at 2:48

3

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When should I use std_logic_vector and when should I use other data types?

I'm new to VHDL and am having trouble figuring out which data types are appropriate to use where. If I understand correctly, for synthesis, all top level entity ports should be declared either std_...

integer port vhdl unsigned signed

Thermel asked 27/5, 2011 at 17:23

4

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VHDL: Finding out/reporting bit width/length of integer (vs. std_logic_vector)?

Say I need a signal to represent numbers from 0 to 5; obviously this needs 3 bits of std_logic to be represented (i.e if MAXVAL=5, then bitwidth= {wcalc "floor(logtwo($MAXVAL))+1"}). I'm aware I ...

integer logic width vhdl synthesis

Dignitary asked 4/3, 2011 at 14:49

8

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vhdl: convert vector to string

How can I convert a std_logic vector, bit_vector or any other vector to string? Signal a,b : UNSIGNED(7 DOWNTO 0); SIGNAL x,y,z : BIT_VECTOR(7 DOWNTO 0); ... report "value: " & BIT_VECTOR'Im...

arrays string vector type-conversion vhdl

Psychodrama asked 14/3, 2013 at 10:37

4

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Is it necessary to seperate combinational logic from sequential logic while coding in VHDL, while aiming for synthesis?

I am working on projects which requires synthesis of my RTL codes specifically for ASIC development. Given the case, how much important is it, to separate sequential logic from differential logic w...

vhdl register-transfer-level asic soc

Kopans asked 17/4, 2017 at 12:39

3

Solved

Wait until <signal>=1 never true in VHDL simulation

Below is the code that I am running. My question is why doesn't the 3rd wait until trigger in modelsim? The console output is simply GOT HERE. It never gets to the line GOT HERE 2. I would think th...

vhdl fpga modelsim

Exhilaration asked 9/12, 2013 at 22:2

2

Solved

Passing Generics to Record Port Types

I did recently start to use records for my port definitions, especially if I want to group signals that belong to a certain interface. However, the problem I'm facing here is that I cannot pass, sa...

vhdl

Sutherlan asked 28/10, 2011 at 5:6

5

Solved

How to convert 8 bits to 16 bits in VHDL?

I have an input signal from ADC convertor that is 8 bits (std_logic_vector(7 downto 0)). I have to convert them to a 16 bits signal (std_logic_vector(15 downto 0)) for 16 bits signal processing to ...

vhdl

Chandlery asked 3/7, 2013 at 15:1

4

found '0' definitions of operator "+" in VHDL

At first I wanna point out that this is my first attempt with VHDL so be kind. I want to read the X1 ... X4 inputs and produce the sum of the ones at the output. This my code library IEEE; use IEE...

vhdl

Ravishment asked 27/10, 2014 at 23:18

5

Solved

Comparing a long std_logic_vector to zeros

In simulation this works perfect. Is this is the best way of checking for zeros for a synthesisable code. What would be the resources generated? signal vector_slv : std_logic_vector(2048 downto 0)...

vhdl

Sylviasylviculture asked 25/9, 2013 at 15:12

3

Power function in vhdl

I want to make power function using vhdl where the power is floating number and the number is integer (will be always "2"). 2^ some floating number. I use ieee library and (fixed_float_types.all,...

vhdl modelsim

Avery asked 28/4, 2013 at 19:9

6

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Implementing a FSM in VHDL

Just wondering if I'm implementing a finite state machine in VHDL whether or not I need to state what all of the outputs are in every possible state? Even if I know that some outputs won't change f...

vhdl fsm

Duque asked 14/5, 2011 at 9:47

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