What does "others=>'0'" mean in an assignment statement?

Question

cmd_register: process (rst_n, clk)
begin
   if (rst_n='0') then
    cmd_r<= (others=>'0');
   elsif (clk'event and clk='1') then
    cmd_r<=...;
   end if;
end process cmd_register;

I know "<=" specifies assignment but what is others? And what does => do?

Glycol

eda.org/comp.lang.vhdl/FAQ1.html#aggregates – Monanthous

(not an exact answer, but as this is kind of a FAQ-type question, I thought I'd point you there for starters) – Monanthous

Answer 1

cmd_r is defined as a std_logic_vector, or unsigned or signed signal. let's see how this signal type are defined:

type std_logic_vector is array (natural range <>) of std_logic; 
type unsigned         is array (natural range <>) of std_logic; 
type signed           is array (natural range <>) of std_logic;

Note that these 3 types have the same definition as an array of std_logic items.

The statement "Others => '0'" is a feature of the VHDL when the coder want to defined several items in an array with the same value.

In your example, all item std_logic in the array are set to '0'.

Another application of this statement is to set some items at a specific value and all others at a default value :

cmd_r <= (0      => '1',
          4      => '1',
          others => '0');

In this case, the bit 0 and 4 are set to '1' and all other bits are set to '0'.

One last thing, it's NOT possible to write something like this :

  cmd_r <= (0          => '1',
            4 downto 2 => "111", -- this line is wrong !!!
            others     => '0');

Wallachia

I believe that last bit of code is possible with VHDL-2008. – Monanthous

Answer 2

It just means set all bits to zero!!

Scorpion

Answer 3

( others => '0') is an expression, an aggregate of elements into a composite type.

Without seeing the declaration for cmd_r we can imagine it's an array type, an array type is a composite type (made of one or more elements).

An aggregate combines one or more values as elements into a composite type.

 aggregate ::=
     ( element_association { , element_association } )

Notice the opening and closing parentheses are required.

Those elements can be associated positionally by name for a record type or by index value position for an array type.

 element_association ::=
     [ choices => ] expression

The element association is governed by choices.

 choices ::=  choice { | choice }

The element association can cover more than one choice.

 choice ::=
        simple_expression
     | discrete_range
     | element_simple_name
     | others

A choice can represent one or more elements.

An element simple name is used for a record type or an array type with an index type that is an enumerated type.

others is always the last choice and stands for all the remaining choices for that type. The type can be discovered in an assignment from the target. In some instances the type is required to be supplied explicitly, as in a qualified expression.

The element association others => '0' stands for all other elements of the type of the aggregate. In this case the type and subtype of cmd_r, where a subtype indication specifies a range index of elements of a std_logic_vector.

The expression '0' is required to be of the element type, and the aggregate (others => '0') stands for a value of the subtype of cmd_r comprised of '0''s for each of the elements of cmd_r in this case.

Holliman

Answer 4

The expression (others=>’O’) means that all elements are assigned to ’0’.
If cmd_r is 8 bit then it will assign 00000000 to cmd_r. If cmd_r is two dimensional then the same thing will be (others =>(others =>'0')).

Centeno

seems like extra syntactic noise. Why not just allow cmd_r<= '0' – Gregorio

This will create an ambiguity. Sometime this will assign just the LSB to zero. I had a code in which this happened. So I always insure that when a vector is presented and if it should be zero then no lose syntax. Just to avoid extra debugging work. – Centeno

@S.N. Not sure that it will compile. You have to explicit the assignation of all the wires. – Primitivism

If cmd_r is declared as: signal cmd_r : unsigned (7 downto 0), can I still use: cmd_r <= (others => '0') to set all the bits in cmd_r to zero? – Dorsman