I am trying to understand how modern CPU works. I am focused on RISC-V. there are a few types of branches: BEQ BNE BLT BGE BLTU BGEU I use a venus simulator to test this and also I am trying to s...

Does the 'softmmu' mean that the virtual machine has a single linear address space available to machine and user mode? Or does it have some virtual memory capabilities that are implemented via soft...

I am working on RISC-V 32I instructions recently. I got a question about NOP instruction, which the specification says it is equal to ADDI x0, x0, 0. However, x0 is not a general register which ca...

I am learning how to write code for a RISC-V processor. I want to store a value of 0xFFFFFFFF into memory / a register. I can extend the 12 immediate bits of addi instruction by adding a lui befo...

I'm reading the book The RISC-V Reader: An Open Architecture Atlas. The authors, to explain the isolation of an ISA (Instruction Set Architecture) from a particular implementation (i.e., microarchi...

Recently, I am working on RV32I base instruction set, and I did not find any instruction looks like LD r1, imm. Thus, I am wondering how assembly programer load an immediate to a register in RV32I ...

I'm trying to learn the RISC-V ISA. Is there a way to simulate RISC-V assembly code just like in MARS for the MIPS ISA?

I don't get how JAL works in RISC-V as I've been seeing multiple conflicting definitions. For example, if I refer to this website: https://rv8.io/isa.html It says that: JAL rd,offset has the 3rd ar...

I am new to RISC-V. I am having trouble comprehending when to write PC (Program Counter) relative instructions and when to write PC absolute instructions. For example, an instruction with lui fol...

I am currently studying the specifications for RISC-V with specification version 2.2 and Privileged Architecture version 1.10. In Chapter 2 of RISC-V specification, it is mentioned that "[...]...

The RISC-V specification v2.2 (JAL instruction, page 15) says of the "standard calling convention": The standard software calling convention uses x1 as the return address register and x5 as an a...

While going through the RISC-V Specification I've noticed that the 64-bit version differs from the 32-bit one in the fact, that it Widened the registers to 64-bit Changed the instructions to act ...

Why do we need to set the least significant bit to zero in JALR in RISC-V Instruction set as described in the RISC-V Instruction manual? Is it for alignment propose?

I have downloaded the latest... RISC-V Instruction Set Manual, Volume 1: User-Level ISA ...which is interesting but it never actually gives values for the opcodes/funct3 and other instructi...

While going through the RISC-V ISA, I have seen an instruction in the memory model section (FENCE instruction). What does it mean exactly?

I want to port the rocket chip to a non-Zynq FPGA (an altera Stratix V), a board which doesn't contain an ARM core used to run the riscv-fesvr. How can I go about starting the port? Also, has anyon...

I have started to work with risc-v few days ago, but yesterday I had a problem. The problem is the following: I want to compile code for example for the RV32I base integer instruction set and I w...

I'm confused about the RISC-V ABI Register Names. For example, Table 18.2 in the "RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.0" at page 85 specifies that the stack pointer s...

What is RISC-V? Why was it created? What improvements does it have over previous RISC architectures? (This is meant to be a wiki for RISC-V on StackOverflow.)

Can someone explain to me the big differences between ( RISC vs CISC ) vs the RISC-V ISA? I cannot find any relevant difference between CISC and RISC-V on the internet.