I find that in RISC-V, ra is caller saved, in MIPS, ra is callee, which means in RISC-V callee can directly change the value in ra without save, but since ra has changed, how callee return back to ...

The context of this question is the creation of a side-channel resistant implementation of a IEEE-754 compliant single-precision square root for a 32-bit RISC-V platform without hardware support fo...

In Control and Status Registers section of riscv-asm-manual, there is an example: .equ RTC_BASE, 0x40000000 .equ TIMER_BASE, 0x40004000 # setup machine trap vector 1: auipc t0, %pcrel_hi(mtvec) # ...

I want to build my own minimal RISC-V processor for a FPGA. The processor will as simple as possible with only one pipeline. I read the entire RISC-V ISA and there are many standard extensions. So...

The RISC-V current SW privilege level is not set in any CSR. Nevertheless the spec states that "Attempts to access a CSR without appropriate privilege level ... raise illegal instruction". How can ...

On Intel AVX, there is a possibility of branchless code. Instead of branching for case0 or case1, you can compute both cases, and blend the results based on a condition. AVX does this 8 way for flo...

I am trying to compile linux for RISCV Arch using buildroot(busybox). I was using 18.04 and 20.04 previously and had no issues compiling it. Right now, I have upgraded it to 21.10 for building some...

I came across the instruction named jal and jalr while studying RISC-V assembly language. I quite having hard times to understand the differences between jal and jalr. jal x1, X It seems that abo...

I'm learning RISC-V assembly and i need to use array for an exercise that i'm solving; the problem is that the simulator that i'm using(RARS) gave me an error: Error in /home/username/file_name lin...

Let's attempt to define a function that returns the maximum of two values x and y. A sufficient condition for these formulas to be valid is that, for signed integers, –2^30 <= x, y <= 2^30 – ...

I found references to hart on page 35 of the RISC-V 2.1 spec. However, I could not find a definition for hart in this document. Does hart refer to a hardware-thread or something more sinister?

I know store buffer and invalidate queues are reasons that cause memory reordering. What I don't know is if Out-of-Order-Execution can cause memory reordering. In my opinion, Out-of-Order-Execution...

I am looking for a C/C++ toolchain that supports the RISC-V vector extension v1.0 as defined per official spec. Spike appears to support vector rvv1.0, but I am having trouble finding a toolchain t...

I've been trying to learn RISC-V coming from MIPS and initially they don't look to dissimilar, especially the instruction set. Are there any significant differences between the two? Are most of the...

I need to deal with bignum calculation (addition and subtraction, but I treat subtraction as equivalent to signed addition) on RISC-V and the situation is a bit complicated. What I gather from half...

I've written and compiled a RISC-V Linux application. I want to dump all the instructions that get executed at run-time (which cannot be achieved by static analysis). Is it possible to get a dy...

I am new to riscv and I am confused between la and lw. I know that la stands for load address and lw stands for load word. If address of VAL is 0x100 and data value of VAL is 0x11 should x3 stores...

I am trying to build a hello world program using Clang (version 12.0.1) for RISC-V architecture. I have installed it with LLVM (version 12.0.1) with the following setup: cmake -G "Unix Makefil...

The Berkeley implementation of RISC-V is called Rocket Chip and it is written in a hardware language called Chisel. Chisel is object oriented, and it has been difficult for the people on our team t...

When setting the mstatus.mpp field to switch to supervisor mode, I'm getting an illegal instruction exception when calling mret. I'm testing this in qemu-system-riscv64 version 6.1 with the riscv64...

I've written a single-cycled CPU in Chisel3 which implements most of the RV32I instructions (except CSR, Fence, ECALL/BREAK, LB/SB, which may be included later). The instructions are currently hard...

For RISC-V, does the stack pointer point at the last data that was pushed on the stack, or the next free address location for the stack? When the stack pointer is being initialized at the very begi...

I am currently using clang11 on ubuntu to compile any c/c++ code and it works fine but when I tried to compile any code (including any standard library) to assembly code for any specific target lik...

I would like to store the result of a C expression into register a0 in a RISC-V program using GCC (for the sake of the examples below, suppose there is a volatile int val = 42 or similar). I am abl...

LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the U-immediate value in the top 20 bits of the destination register rd, filling in the lowest ...