What is meant by the FENCE instruction in the RISC-V instruction set?

Question

While going through the RISC-V ISA, I have seen an instruction in the memory model section (FENCE instruction). What does it mean exactly?

Culley

Answer 1

I've found one case when using FENCE instruction is just necessary. Example:

1. Some module in a SoC generates interrupt by writting value into CSR 0x783 (MIPI) via HostIO bus.
2. Firmware jumps to the interrupt handler.
3. Handler tries to reset 'pending' bit in a user implemented device by writting 1 into register.
4. Such operation was compiled as a 'store' instruction with immediate value =1.
5. As result, if I don't implement FENCE at the beginning of the handler I have some garbage value instead of proper immediate argument of the instruction.

Gulfweed

Answer 2

The RISC-V ISA uses a relaxed memory model where the order of loads and stores performed by one thread may be different when seen by another. This is done to enable techniques to increase memory system performance.

For example, Thread 1 may execute:

• Load A
• Store B
• Store C

But Thread 2 could see the loads and the stores out of order with regard to the first thread:

• Store C
• Load A
• Store B

The FENCE ensures that all operations before the fence are observed before any operation after the fence. So if the above changed to:

Thread 1:

• Load A
• Store B
• FENCE
• Store C

Then Thread 2 would be guaranteed to see the load to A and the store to B before the store to C, but still could see the store to B before the load of A.

Thread 2:

• Store B
• Load A
• Store C

Source: RISC-V ISA (Section 2.7 page 20)

Incorporating Chris P's comment:

I/O (I and O flag) and memory accesses (R and W) can be controlled separately with the FENCE instruction For example: You can control that only memory writes should be ordered by FENCE but memory reads and I/O operations are unaffected by FENCE. For this, the PW and SW bits should be set. If only PW (predecessor write) is set, then FENCE will ensure, that all memory writes before FENCE are also observed by other harts (threads) before FENCE, but memory writes after FENCE can also be observed before.

Swingle

Can you elaborate more on the meaning of the flags this instruction takes as input? Specifically the predecessor and successor sets of I, O, R, and W flags and how their various settings affect the behavior of FENCE? – Rooky

@SamuelA.FalvoII I/O (I and O flag) and memory accesses (R and W) can be controlled separately with the FENCE instruction For example: You can control that only memory writes should be ordered by FENCE but memory reads and I/O operations are unaffected by FENCE. For this, the PW and SW bits should be set. If only PW (predecessor write) is set, then FENCE will ensure, that all memory writes before FENCE are also observed by other harts (threads) before FENCE, but memory writes after FENCE can also be observed before. – Righthand

If I am compiling software for RISC-V, should I target an architecture with or without fencing? I am targeting general-purpose RISC-V processors, so the "G" extension seems like a convenient option to target, but around the Internet I see IMAFD everywhere (which is G without fencing) so I'm wondering if that's a better target. – Abrasive

@AaronFranke FENCE is included in the base RISC-V ISA (per risc-v-spec-v2.2, page 20) – Precipitant

@Righthand Can you add this to original answer. Its a necessary piece of information – Malapropos

@Malapropos - Comment added. – Swingle