What is RISC-V and how does it compare to previous RISC architectures?

Question

What is RISC-V? Why was it created? What improvements does it have over previous RISC architectures?

(This is meant to be a wiki for RISC-V on StackOverflow.)

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Answer 1

RISC-V is an instruction set architecture (ISA) that is open, clean, and easily extensible (and also realistic).

It was originally started as a clean-slate ISA at UC Berkeley for building research processors. A 64b ISA, with no legacy baggage, floating point IEEE754-2008 support, and enough opcode space for research extensions was required.

Compared to previous RISC ISAs, there are no branch delay slots or register windows. Branch instructions are full register-register magnitude compares (instead of compare against zero or equality only). Also, it is BSD-licensed, so others can freely implement their own processors.

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