Differences between RISC-V and others ISAs

Question

Can someone explain to me the big differences between ( RISC vs CISC ) vs the RISC-V ISA? I cannot find any relevant difference between CISC and RISC-V on the internet.

Stomato

RISC - Reduced Instruction Set Computer and CISC - Complex Instruction Set Computer. – Icelander

I guess you have at least read wikipedia articles on RISC/CISC. RISC-V is ISA designed mostly for educational purpose. Details can be found in inst.eecs.berkeley.edu/~cs152/sp12/handouts/riscv-spec.pdf. – Spodumene

Answer 1

RISC-V is a new ISA developed at Berkeley to assist in both research and education. It is open, clean, and easily extensible (and also realistic).

A common problem with building research processors is finding an ISA to use that isn't muddled with legacy decisions (delay slots, register windows), isn't protected by patents, and has enough opcode space to explore new instructions/accelerators/processor micro-architectures.

A public release (v2.0) is coming soon, and you can read the current draft at riscv.org. (disclosure: I use RISC-V for my own research, and I sit next to the guys who designed and implemented it). [Edit: It has been officially released as of May 2014 (http://riscv.org/download.html#tab_isaspec)].

In terms of comparison to other ISAs, it is probably most similar to MIPS and ARMv8 (RISC-V v1.0 was actually released before ARMv8 came out). It is a load-store architecture (no register-memory operations like x86, except for a set of AMOs). There are some parts of RISC-V that you could argue is "CISC-y", like the option to support compressed instructions for energy reasons (16b) or larger instructions for even more opcode space (variable instruction length is an optional superset, the base-set of the ISA is all 32b instructions). Also FMAs feel a bit CISC-y too, with three source operands and two operations. But now we're meandering into opinion territory of what's CISC and what's RISC. At the end of the day, RISC-V is a very easy to decode ISA, and all instructions in it are easy to schedule and do hazard checking on (no weird side-effects, as you would find in CISC ISAs).

Newell

FMA isn't really implemented as separate a*b + c operations; remember it has to avoid any rounding of the a*b result; that's part of the point. Also remember that multiply can be broken down into additions of partial products, so adding into an existing operand instead of zero barely adds anything to the cost. (This part of the argument works better for integer multiply-accumulate (MAC) instructions, where there's no exponent shift). So most of the cost is in supporting 3-input instructions for scheduling / hazard detection to track. – Jaclyn

Answer 2

RISC-V is a research ISA, but there are multiple FPGA softcore implementations already, not to mention simulators. It's most similar to MIPS (and NIOS 2, MicroBlaze, Alpha, LM32, ...) but one important difference is how branches are handled:

Visible branch delay slots have largely been recognized as complicating super scalar implementations and are challenging for compilers to fill. With advances in branch prediction, they are no longer needed thus RISC-V omits them. Furthermore, as branches can be resolved later in the pipeline RISC-V's conditional branches can compare any two registers for equality as well as ordering.

Recidivism

I'd just like to add that according to their user level manual found at (riscv.eecs.berkeley.edu), they've also fabbed a half dozen designs implementing RISC-V (for research purposes). – Newell

MIPS64r6 (2014) rearranged the opcode space and provides no-delay-slot branch instructions. But it does still have to support legacy delayed branches, complicating the uarch and the exception-return format. – Jaclyn