I am learning assembly for x86 using DosBox emulator. I am trying to perform multiplication. I do not get how it works. When I write the following code: mov al, 3 mul 2 I get an error. Although,...

I'm looking through this tutorial: http://www.cl.cam.ac.uk/freshers/raspberrypi/tutorials/os/ok01.html The first line of assembly is: ldr r0,=0x20200000 the second is: mov r1,#1 I thought ld...

As far as I know, there is no instruction in SSE/AVX for loading an immediate. One workaround is loading a value to a normal register and movd, but compilers seem to think this is more costly than ...

My understanding is that immediate parameters in ARMv8 A64 assembly can be 12 bits long. If that is the case, why does this line of assembly code: AND X12, X10, 0xFEF Produce this error (when c...

LUI (load upper immediate) is used to build 32-bit constants and uses the U-type format. LUI places the U-immediate value in the top 20 bits of the destination register rd, filling in the lowest ...

In the RISC-V Instruction Set Manual, User-Level ISA, I couldn't understand section 2.3 Immediate Encoding Variants page 11. There is four types of instruction formats R, I, S, and U, then there i...

First I am a little bit confused with the differences between movq and movabsq, my text book says: The regular movq instruction can only have immediate source operands that can be represented as 32...

Firstly a trivial mathematical fact: given integers n and m, we have n < m if, and only if, n <= m - 1. GCC seems to prefer immediate values of smaller absolute value. Hence, when m is known...

I am trying to assemble some 64-bit code and the assembling fails on the line: addq $0xffffff7fc0005000, %rax with the error: Error operand type mismatch for `add' The first operand is a 64...

Recently, I am working on RV32I base instruction set, and I did not find any instruction looks like LD r1, imm. Thus, I am wondering how assembly programer load an immediate to a register in RV32I ...

I just begin to study ARM assembly language, and am not clear about how to use MOV to transfer an immediate number into a register. From both the ARM reference manual and my textbook, it's said tha...

I've read a few tutorials and examples, but I cannot wrap my head around how the MUL instruction works. I've used ADD and SUB without problems. So apparently this instruction multiplies its operand...

I have this risc v code : lui S0, 0x1234 ori S1, S0, 0x5678 add S2, S1, S1 and the question asks me, "What does the register S2 hold?" The question explains that lui and I quote: "L...

After reading this stack overflow answer, and this document, I still don't understand the difference between movq and movabsq. My current understanding is that in movabsq, the first operand is a 64...

I want to load 1 32 bit hexadecimal directly into a register using arm assembly. mov r1,#0x6c617669 This cannot be used because from this instruction we can only load 8 bit values. So I have loa...

I'm talking about data movement instructions in the x86-64 Intel architecture. I have read that the regular movq instruction can only have immediate source operands that can be represented as 32-bi...

Is there is a standard or recommendation for how the addi instruction (and others) should be interpreted in assembly, when hexadecimal immediate values are used? Example: addi $t0, $zero, 0xffff ...

In MIPS assembly, what is the benefit of using addiu over addi? Isn't addiu unsigned (and will ruin our calculations?)

I have this line of code: X DC.W 5 This means basically X = 5 But shouldn't be X DC.W #5 ? When using MOVE I need always # MOVE.B #1,VAR

In the systems software course that I have this semester, we are being taught assemblers and other system software. While reading across the course I came across the topic of LITERALS. There was a...

At my 64bit Intel machine following code works: mov rdi, 1 << 40 add r10, rdi and this quite equivalent looking one produces a warning and doesn't work: add r10, 1 << 40 Should I ...

For some reason, when I try to compile this bit of code, the compiler says syscall.s:72:invalid constant (0x172) after fixup: .globl _mach_msg_trap$MACH _mach_msg_trap$MACH: stmfd sp!, {r4,r7} m...