I have been curious about this for awhile since compression is used in about everything. Are there any basic compression support instructions in the silicon on a typical modern CPU chip? If not...

How is it that an executable can work on both AMD and Intel systems? Aren't AMD's and Intel's instruction sets different? How does the executable work on both? How exactly do they compile the files...

Background It is well known that the exact product of two floating point numbers is not always a floating point number, but the error exact(a*b) - float(a*b) is. Some codes for exact multiplicatio...

Most of the assembly code is terminate by the following instructions MOV AH, 4CH INT 21H What does it mean by "MOV AH, 4CH" ?

I'm just starting to learn ARM and I'm having trouble understanding what the load and store instructions do exactly. Load instructions: ldrsb ldrb ldrsh ldrh ldr Store instructions: strb strh str ...

I've been trying to understand assembly language code generated by GCC and frequently encounter this instruction at the start of many functions including _start(), but couldn't find any guide expla...

In instruction encoding Default sizes are: operand size is 32 bit address size is 64 bit We can use the legacy prefix: 0x66 – Operand-size override prefix to make operand size 16. What if I want...

An analysis on https://ridiculousfish.com/blog/posts/benchmarking-libdivide-m1-avx512.html finds that the new Apple CPU has spent a lot of resources making integer division massively faster. This i...

I am trying to understand assembly to be able to solve a puzzle. However I encountered the following instructions: 0x0000000000401136 <+44>: cmpl $0x7,0x14(%rsp) 0x000000000040113b <+49&gt...

They're one of the simplest "instructions" you could perform on a computer (they're the first ones I'd personally implement) Performing NOT(AND(x, y)) doubles execution time AND dependen...

I wrote the following piece of code that steps through /bin/ls and counts its instructions: #include <stdio.h> #include <sys/ptrace.h> #include <sys/types.h> #include <sys/wait...

I have the following MIPS code (for swapping adjacent elements from an array) from a class slide: muli $2, $5,4 add $2, $4,$2 lw $15, 0($2) lw $16, 4($2) sw $16, 0($2) sw $15, 4($2) jr $31 This ex...

I've been struggling with understanding the ASCII adjust instructions from x86 assembly language. I see all over the internet information telling me different things, but I guess it's just the sam...

recently i checked the Instruction Set for an ARM Cortex-M3 processor. For example: ADD <Rd>, <Rn>, <Rm> What do those abbriviations mean exactly? I guess they mean different ...

I'm using libdis, the x86 disassembler library from the bastard, and I'm trying to find out which instructions access memory. With reference to these two instructions: mov eax, [ebx + 10] lea eax...

In ARM64 assembly code, when does register number 31 mean XZR and when does it mean SP?

In the context of the Intel® 64 and IA-32 Architectures Software Developer Manuals, what exactly is a processor "hint?" I see it in a few sections: In the description of PREFETCHWT1 -Pre...

I'm doing something about function safety. I need verify some X86 CPU instructions, such as LFENCE, SFENCE and MFENCE. Now I can experience MFENCE according to Intel SDM chapter 8.2.3.4 "loads may...

I'm trying to learn assembly (so bear with me) and I'm getting a compile error on this line: mov byte [t_last], [t_cur] The error is error: invalid combination of opcode and operands I suspec...

I'd like to statistically profile my C code at the instruction level. I need to know how many additions, multiplications, divisions, etc I'm performing. This is not your usual run of the mill code...

I am wondering if there is anything at the assembly level in x86-64 that allows you to sleep/wait, such that no instructions are run until the wait is done. I have seen the WAIT and PAUSE instructi...

ADRP Address of 4KB page at a PC-relative offset. ADRL Load a PC-relative address into a register. It is similar to the ADR instruction. ADRL can load a wider range of addresses than ADR b...

I don't get how JAL works in RISC-V as I've been seeing multiple conflicting definitions. For example, if I refer to this website: https://rv8.io/isa.html It says that: JAL rd,offset has the 3rd ar...

I'm here to ask you some stuff about VS2017. In the past I had used WinAsm for MASM and I never got problems with it. However, when I'm trying to do something with MASM in VS2017, I always gonna g...

It may be a stupid question but I'm not able to find a clear explanation about these 2 phases of an instruction life. My initial thinking was that they are synonymous but I'm not sure anymore. I st...