opcode Questions
2
Solved
Does anyone know why the JSR/RET bytecode pair is deprecated in Java 6?
The only meaningful explanation I found on the net was that they made code analysis by the runtime harder and slower to perf...
Skinner asked 3/5, 2011 at 14:37
5
Solved
What does a \ do in PHP?
For example, CSRF4PHP has \FALSE, \session_id, and \Exception:
public function __construct($timeout=300, $acceptGet=\FALSE){
$this->timeout = $timeout;
if (\session_...
Slumberous asked 25/1, 2011 at 4:34
2
Solved
I've been looking for a list of the opcodes used in ARM Cortex M3/M4/M4F, without luck.
There are plenty of [online] references to the 32-bit format of ARM instructions.
References to Thumb-2 instr...
Acidhead asked 28/12, 2014 at 13:15
4
Solved
<?php
$show_value = 123;
echo 'sing_quote'.$show_value;
echo "double_quote{$show_value}";
?>
Its opcode is:
1: <?php
2: $show_value = 123;
0 ASSIGN !0, 123
3: echo 'sing_quote'.$...
2
Solved
The invokespecial JVM instruction is used for calling initialisation methods (<init>) when creating new objects. The description of the instruction suggests (but doesn't clarify) that the dec...
1
Solved
Playing around a bit with Turbo Assembler and Turbo Debugger, I was surprised about opcodes. More precisely, I have some assembled binary in which Turbo Debugger disassembles the word
29 C3
...
Domenech asked 22/8, 2021 at 15:0
4
3
Solved
The encoding of
call qword ptr [rax]
call qword ptr [rcx]
is
FF 10
FF 11
I can see where the last digit (0/1) comes from (the register number), but I'm trying to figure out where the second l...
Pilsudski asked 19/3, 2013 at 22:10
3
TL;DR
I tried to make this a short question but it's a complicated problem so it ended up being long. If you can answer any part of this or give any suggestions or tips or resources or anything at...
Yacano asked 30/5, 2013 at 23:56
2
Solved
While building a chip-8 emulator, I ran into the problem where the 2 main sources of chip-8 information seem to differ which has implications for the whole chip-8 interpreter.
On the one side we h...
1
Solved
I've narrowed a problem down to this code
$a = 3;
$a = 3 * $a++;
echo $a; //9
$a = 3;
$a = $a * $a++;
echo $a; //12
Here are VLD opcodes for 1st operation
compiled vars: !0 = $a
line #* E I ...
2
I've been trying to understand the purpose of the 0x40 REX opcode for ASM x64 instructions. Like for instance, in this function prologue from Kernel32.dll:
As you see they use push rbx as:
40 5...
Izzo asked 9/5, 2018 at 18:38
4
Don't be shocked. This is a lot of text but I'm afraid without giving some detailed information I cannot really show what this is all about (and might get a lot of answers that don't really address...
Instal asked 9/6, 2009 at 20:53
1
Solved
I'm writing my own assembler and trying to encode the ADC instruction, I have a question about immediate values, especially when adding 8-bit value into the AX register.
When adding 16-bit value: ...
Kiely asked 10/6, 2019 at 9:51
1
I was going through some disassembly of a CRT library (the SEH prolog in particular) when I suddenly came across this strange instruction bnd ret. Can anyone explain the meaning of the f2 prefix ri...
Stolen asked 27/3, 2017 at 22:25
1
Solved
Why was nop assigned to 0x90 on intel x86 assembly?
Intuitively I would expect that 0x00 would map to nop (which is also xchg eax, eax at intel x86) as it is the case for ARM A32 and some other ar...
Unready asked 1/5, 2019 at 19:54
1
Solved
I am reading the ia-32 instruction format and found that ModR/M is one byte if required, but how to determine if it is required, someone says it is determined by Opcode, but how? I want to know the...
Cookhouse asked 23/3, 2019 at 9:44
2
Solved
4
I have an assembly program that has the following code.
This code compiles fine for a intel processor. But, when I use a PPC (cross)compiler, I get an error that the opcode is not recognized. I am ...
1
I know that there are libraries that can "parse" binary machine code / opcode to tell the length of an x86-64 CPU instruction.
But I'm wondering, since CPU has internal circuitry to determine this...
Deceptive asked 26/7, 2018 at 19:25
7
Solved
According to the opcodes it should be 12. Am I getting it wrong?
number of ops: 8
compiled vars: !0 = $x
line #* E I O op fetch ext return operands
------------------------------------------------...
1
Solved
looking at http://ref.x86asm.net/coder32.html I found two opcodes that match for the statement
xor eax,eax
1) opcode 31 XOR r/m16/32 r16/32
2) opcode 33 XOR r16/32 r/m16/32
both refers to 32bi...
Orelia asked 14/5, 2018 at 17:52
2
Solved
IDM says the memory op uses SS segment if EBP is used as base register. As a result, [ebp + esi] and [esi + ebp] references SS and DS segments, respectively. See NASM's doc: 3.3 Effective Address.
...
Heathendom asked 8/4, 2018 at 19:19
1
In 32-bit mode Intel solves the VEX prefix vs LDS/LES conflict by inverting the high bits of register extension, because the mod field of ModRM byte can't be 11b
The VEX prefix's initial-byte va...
Juliojulis asked 18/2, 2018 at 15:20
3
Solved
For the following code
<?php
$a=1; $b=$a++; var_dump($b);
$a=1; $b=$a+$a++; var_dump($b);
$a=1; $b=$a+$a+$a++; var_dump($b);
$a=1; $b=$a+$a+$a+$a++; var_dump($b);
$a=1; $b=$a+$a+$a+$a+$a++; va...
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