In this Wikipedia article about register preservation I read that the caller function is responsible for some registers (to keep their previous data from being changed) and the callee for others. M...

I have the following simple C code: void main(){ int A = 333; int B=244; int sum; sum = A + B; } When I compile this with $riscv64-unknown-elf-gcc code.c -o code.o If I want to see the...

In the RISC-V Instruction Set Manual, User-Level ISA, I couldn't understand section 2.3 Immediate Encoding Variants page 11. There is four types of instruction formats R, I, S, and U, then there i...

We know that jal specifies a 21-bit offset. However, it does not encode a 21-bit offset but a 20-bit one. The reason is that the least significant bit of an address is always zero because the small...

I am very new to bare metal programming and have never delt with interrupts before, but I've been learning on a RISC-V FE310-G002 SOC powered dev board. I've been reading about the RISC-V WFI (Wait...

Introduction: I bought a Longan Nano evaluation board equipped with a GD32VF103 Risc-V MCU. I can run the video player demo, and compile and load working code using VS Code, PlatformIO and the DFU ...

I see the standard way of exiting RISC-V exception handler is update mepc to mepc+4 before mret. But won't this cause problem if the next instruction is only 2-bytes long in compressed instruction...

I am looking for how a RISC-V processor processes interrupt requests. I looked at the Instruction Set Manuals and information on the internet. The focus is on explaining exactly what the title set...

When I reading RISC-V User-Level ISA manual,I noticed that it said that "OpenRISC has condition codes and branch delay slots, which complicate higher performance implementations." so RISC-V don't h...

In the RISC-V Unpriviliged spec V20191213, the following is stated, (page 21) The unconditional jump instructions all use PC-relative addressing to help support position-independent code. Loo...

What is the simplest way to work with big-endian values in RISC-V at the assembly language level? That is, how to load a big-endian value from memory into a register, work with the register value i...

I want to compile a simple program "int main(){return 0;}" to RISC-V processor. LLVM/Clang version is 9.0 and I want to run the compiled program with a RISC-V simulator like this https://github.com...

I was trying to read RISC-V assembly generated by gcc and I found that gcc creates sequence of auipc+jalr for some function calls and I don't understand how it works. Here's a simple example. Consi...

I am currently working on implementing RV32I Base Instruction Set. I had a question about ADDI instruction. In the manual, how to understand this clause "ADDI rd, rs1, 0 is used to implement the ...

Most instructions in RISC-V assembler order the destination operand before the source one, e.g.: li t0, 22 # destination, source li t1, 1 # destination, source add t2, t0, t1 # destination, source...

What is the calling convention for a syscall in a program that runs under the RISC-V pseudo-kernel (pk) or Linux? Looking at the code generated by the riscv-gnu-toolchain the rules seem to be: s...

I don't really understand the difference between a normal FENCE in RISC-V (has been answered here: What is meant by the FENCE instruction in the RISC-V instruction set?) and the FENCE.TSO. The manu...

Load and store instructions have the same requirements for encoding: two registers and a 12-bit immediate. However store instructions (sb, sh, sw) have a dedicated format that is called S-type wher...

I am trying to load mstatus with another register t1. lw t1, mstatus # load mstatys register into t1 xori t1, t1, 0x8 # xor mstatus to set 3rd bit and leave everything else as is lw mstatus, t...

I am reading a book "Computer Organization and Design RISC-V Edition", and I came across the encoding for S-B and U-J instruction types. Those types I have mentioned above has strange encoded imme...

I converted a very simple C program to an assembly file (Here, RISC-V ISA), and there were some operations done on the stack pointer that I did not understand. The C program : int main() { int ...

In the RISC-V specification, it is written that the immediates in JAL and JALR instructions are converted to jump offsets as : Sign extend the given immediate to XLEN bits. Set the LSB to zero. ...

I am currenty converting the nacl library to risc-v. I already have poly1305 working. I am trying to do this using the risc-v core instruction set, so I don't have a multiplier. The algorithm for P...

I am trying to create a boot program for RISC-V based boards. I am following this guide, and adapting it for riscv. osdev The problem I'm having is translating this instruction. times 510 -( $ - $...

GCC for Risc-V produces nop instructions after call instructions by default: $ cat test.c void g(); void f() { g(); } $ riscv64-unknown-elf-gcc -S test.c -o - [...] f: addi sp,sp,-16 sd ra,8(s...