It is unclear to me how the compiler will automatically know to compile for 64-bit when it needs to. How does it know when it can confidently target 32-bit? I am mainly curious about how the com...

A question I have on Problem 5.5 of the book Computer Systems: A Programmer's Perspective about clock cycles required to perform arithmetic operations: For context, clock cycles required for...

This is the original tests. The figure shows that CPU=8 in Intel Core i9-12900K has the fastest access to all other cores. Therefore, I am wondering what makes it happen. Besides, I am also curious...

I am aware of a few tools that measure power consumption of programs, such as powerTOP, RAPL and the like. However, I was wondering if there exists some kind of benchmark such as Agner Fog's benchm...

Consider massiveley SIMD-vectorized loops on very large amounts of floating point data (hundreds of GB) that, in theory, should benefit from non-temporal ("streaming" i.e. bypassing cache...

In MESI protocol you write to the cache line only when holding it in the Exclusive/Modified state. To acquire the Exclusive state, you send an Invalidate request to all the cores holding the same c...

While trying to benchmark implementations of a simple sparse unit lower triangular backward solve in CSC format, I observe strange behavior. The performance seems to vary drastically, depending on ...

Can masking improve the performance of AVX-512 memory operations (load/store/gather/scatter and non-shuffling load-ops)? Seeing as masked out elements don't trigger memory faults, one would assume ...

Is there a way to identify the iOS device CPU architecture in runtime? Thank you.

I found references to hart on page 35 of the RISC-V 2.1 spec. However, I could not find a definition for hart in this document. Does hart refer to a hardware-thread or something more sinister?

As part of my app I'm using the NDK and was wondering if it's worth bundling x86 and mips binaries alongside the standard ARM binaries. I figured the best way would be to track what my users actua...

Before you laugh at me: I want to ask arithmetic operation is done in ALU unit or accumulator. I read a book it says accumulator is a register for doing arithmetic. This Accumulator said Withou...

Short version I would like to know the technical reasons why do Docker images need to be created for multiple architectures. Also, it is not clear whether the point here is creating an image for e...

Essentially, how does 4Gb turn into 4GB? If the memory is addressing Bytes, should not the possibilities be 2(32/8)?

Is there a way that we can write some code to produce a "spurious failures" for the "weak" version of compare_exchange? While the same code should work well for compare_exchange...

I understand how things like numbers and letters are encoded in binary, and thus can be stored as 0's and 1's. But how are functions stored in memory? I don't see how they could be stored as 0's a...

CPUs intended to provide high-performance number crunching, end up with some kind of vector instruction set. There are basically two kinds: SIMD. This is conceptually straightforward, e.g. instead...

It's clear why a 16-bit floating-point format has started seeing use for machine learning; it reduces the cost of storage and computation, and neural networks turn out to be surprisingly insensitiv...

I was reading Agner Fog's optimization manuals, and I came across this example: double data[LEN]; void compute() { const double A = 1.1, B = 2.2, C = 3.3; int i; for(i=0; i<LEN; i++) { dat...

There are the words in linux/Documentation/x86/x86_64/5level-paging.rst Original x86-64 was limited by 4-level paging to 256 TiB of virtual address space and 64 TiB of physical address space. I k...

I've been wondering.. It's called SIMD as in single instruction multiple data. So why does it have single data instructions? For example, vaddss is the single data equivalent of the multiple data v...

This question is a spin-off of the one posted here: Measuring bandwidth on a ccNUMA system I've written a micro-benchmark for the memory bandwidth on a ccNUMA system with 2x Intel(R) Xeon(R) Platin...

In the book Computer Systems: A Programmer's Perspective, the Exercise 5.5 shows a piece of code to compute the value of a polynomial double poly(double a[], double x, int degree) { long in...

After serious development, CPUs gained many cores, gained distributed blocks of cores on multiple chiplets, numa systems, etc but still a piece of data has to pass through not only L1 cache (if on ...

I know store buffer and invalidate queues are reasons that cause memory reordering. What I don't know is if Out-of-Order-Execution can cause memory reordering. In my opinion, Out-of-Order-Execution...