I am trying to understand a simple example and wonder why I don't see more false sharing than reported by perf c2c. In my example (a matrix multiplication), two instances could cause false sharing ...

I just started to work with Android Studio and I stuck with one problem . When I try to download a system image and create an AVD I get this error " Install Google APIs Intel x86 Atom System I...

Intel manual says that local APIC registers are memory mapped to a 4KB region, with the default address being FEE00000H. This address can be modified using IA32_APIC_BASE MSR. Quoting SDM Vol 3, s...

I am on the hook to analyze some "timing channels" of some x86 binary code. I am posting one question to comprehend the bsf/bsr opcodes. So high-levelly, these two opcodes can be modeled as a "loo...

I'm building a PC with the new Intel I7 quad core processor. With hyperthreading turned on it will report 8 cores in Task Manager. Some of my colleagues are saying that hyperthreading will make th...

I tried to install my app into Android L Preview Intel Atom Virtual Device, it failed with error: INSTALL_FAILED_NO_MATCHING_ABIS What does it mean?

This question used to be a part of this (now updated) question, but it seems like it should be another question, since it didn't help to get an answer to the other one. My starting point is a lo...

I would like to implement the following function using SSE. It blends elements from a with packed elements from b, where elements are only present if they are used. void packedBlend16(uint8_t mask...

I use GoogleColab to test data stuctures like chain-hashmap,probe-hashmap,AVL-tree,red-black-tree,splay-tree(written in Python),and I store very large dataset(key-value pairs) with these data...

When I am using intel_pstate, I found that I can not change the cpu frequency with command: sudo cpupower frequency-set -f SomeValue I know the reason is that intel_pstate's governors (powersave a...

I've been reverse engineering the EnterCriticalSection function on Windows 10 and found this interesting spin-loop: It goes: lbl_loop: mov ecx, [rsp+60h] mov ecx, [rsp+60h] mov ecx, [rsp+60h] pau...

Following this and this posts, I'm compiling the main.c code on this GitHub Gist. Running CMake command find_package(OpenCL REQUIRED) I get this: -- Looking for CL_VERSION_2_2 - found -- Found ...

This is frustrating af. My problem seems not to be unique as you can see, there are a lot of similar issues opened here in SO but after playing trial and error for i-dont-know-how-many-hours i give...

I have to make a recommendation to management regarding whether or not we should spend the extra money to purchase new computers with Intel i7 CPUs (i7 950s) or whether we should buy Intel Core 2 Q...

In the document titled Data Operand Independent Timing Instruction Set Architecture (ISA) Guidance Intel is introducing a new IA32_UARCH_MISC_CTL MSR where toggling bit 0 enables the "Data Ope...

In the technical overview published by Intel, "Sub-NUMA Clustering" and "Hemisphere and Quadrant Modes" are described separately. But the main difference between them is not cle...

I stumbled upon a peculiar performance issue when running the following c++ code on some Intel Xeon processors: // array_a contains permutation of [0, n - 1] // array_b and inverse are initialized ...

I'm developing on SBC (which have Intel I7 3ed or 4ed, and doesn't have external GPU) I'm using linux. I want to take the advantage of Intel processor graphics . I thought to learn developing with ...

I installed Android Studio and I had no problems with that. However, when I tried to run the emulator, it said that Intel HAXM was not installed. So I found the installer, ran it, and it even thou...

I have an Intel Sapphire Rapids CPU with 56 cores. By default, SNC is not enabled. When core 0 accesses a certain memory address A, I think the following will happen: One of the cache agent is acc...

I have seen the related question including here and here, but it seems that the only instruction ever mentioned for serializing rdtsc is cpuid. Unfortunately, cpuid takes roughly 1000 cycles on my ...

I am trying to find out what an x86 processor does when it encounters a store conditional instruction. For instance does it stall the front end of the pipeline and wait for the ROB buffer to become...

When talking about multi-threading, it often seems like threads are treated as equal - just the same as the main thread, but running next to it. On some new processors, however, such as the Apple &...

I'm trying to use the Intel HAX x86 emulator for Windows (8, if that matters). I installed everything and created an AVD for the android version, and everything appears correct, but when I run it, ...

The motivation for this question The unaligned load is generally more common to use. The developer should use the aligned SIMD load when the address is already aligned. So I started to wonder if th...