Given some Random.exe on Windows, how can I determine its CPU architecture eg Intel/ARM, and its bitness eg 32 or 64. Is there a property in File Explorer, some other tool, or programatic meth...

given this code lp: vpaddq ymm0, ymm1 vpaddq ymm3, ymm4 add rbx, rax add rcx, rax vpaddq ymm1, ymm2 vpaddq ymm4, ymm5 sub rax, 0xA jge lp according to the https://uica.uops.info this is ...

Need to create a script to check to see if the kernel is in PAE mode or not. Surely, it is not enough to just check if the /proc/cpuinfo flags have this 'pae' setting. We must know if the PAE mech...

In the document titled Data Operand Independent Timing Instruction Set Architecture (ISA) Guidance Intel is introducing a new IA32_UARCH_MISC_CTL MSR where toggling bit 0 enables the "Data Ope...

When disassembling an executable I encountered the cmove instruction. I've already searched on the Internet but I've only found that it's a conditional move, and if the source and destination are e...

I am currently looking for answers to why gcc generates strange instructions like "rep ret" in the generated assembly code. I came across a question on Stack Overflow where someone raised...

I am taking a course of system tools and architecture in my University and the first class is about how CPU and RAM talks and how CPU process the data. As explained by the Prof, CPU has an ALU (Ari...

Since amd zen 4 has only 256bit wide operations on vector data, the following diagram from chipsandcheese's Zen 4 article shows 6 FP pipelines (4 ALU and 2 memory): Each FMA does 1 multiplication ...

In the technical overview published by Intel, "Sub-NUMA Clustering" and "Hemisphere and Quadrant Modes" are described separately. But the main difference between them is not cle...

Changing add to adc in the highlighted line below significantly improves performance. I find it very counter-intuitive, since add has more ports to execute and it does not depend on flags. CPU: Int...

I stumbled upon a peculiar performance issue when running the following c++ code on some Intel Xeon processors: // array_a contains permutation of [0, n - 1] // array_b and inverse are initialized ...

Some CPUs (notably x86 CPUs) feature a parity flag on their status register. This flag indicates whether the number of bits of the result of an operation is odd or even. What actual practical purp...

I have an Intel Sapphire Rapids CPU with 56 cores. By default, SNC is not enabled. When core 0 accesses a certain memory address A, I think the following will happen: One of the cache agent is acc...

I am trying to find out what an x86 processor does when it encounters a store conditional instruction. For instance does it stall the front end of the pipeline and wait for the ROB buffer to become...

In xcode which is the developement environment for iOS. When creating a new project. Build settings states that it supports armv7, armv7s and arm64 architectures. The following chart shows apple ...

I came across this code emission for x64 were "Atomic Load" is using a simple movq whereas "Atomic Store" is using xchgq. This link explains that Atomic Load/Stores on aligned a...

Cache lines are often 64 bytes, other sizes also exist. My very simple question is: is there any theory behind this number, or is it just the result of the vast amount of tests and measurements th...

I remember in an assembly class, we learned the m68k processor, and there were 3 kinds of shifts you could do. Linear shift, circular shift, and circular shift with extend. The last one, circular ...

In languages like C, unsynchronized reads and writes to the same memory location from different threads is undefined behavior. But in the CPU, cache coherence says that if one core writes to a memo...

Suppose an external interrupt request is made to 8086. Processor will handle the interrupt after completing the current instruction being executed (if any). Before handling of the interrupt, the st...

I've been told and have read from Intel's manuals that it is possible to write instructions to memory, but the instruction prefetch queue has already fetched the stale instructions and will execute...

In Paul McKenny's famous paper "Memory Barriers: A Hardware View for Software Hackers" 3.3 Store Buffers and Memory Barriers To see the second complication, a violation of global memory ...

I am using Intel(R) Core(TM) i5 CPU M 560 @ 2.67GHz as I found out from cat /proc/cpuinfo. But I want to know exact hierarchy like how many sockets are there, and how many cores are there per socke...

NOT on a register holding binary 11111111 will produce 00000000, but ZF will still have its old value, so it might not be 1 even though the output value is all zero. XOR reg, -1 would do the same t...

I read that the multithreading is the feature that a single core can manage many threads (not in parallel) and the benefit is that the CPU is always working. For the Hyperthreading that a single co...