Does Cache Coherence always prevent reading a stale value? Do invalidation queues allow it?

Question

In MESI protocol you write to the cache line only when holding it in the Exclusive/Modified state. To acquire the Exclusive state, you send an Invalidate request to all the cores holding the same cache line.

But is there an micro-architecture where some core will respond with acknowledgement before actually invalidating the cache line? If it's a case, isn't it a violation of Cache Coherence?

The reason I'm asking this question is because I'm confused by this answer - Memory barriers force cache coherency?. It says:

Placing an entry into the invalidate queue is essentially a promise by the CPU to process that entry before transmitting any MESI protocol messages regarding that cache line. So invalidation queues are the reason why we may not see the latest value even when doing a simple read of a single variable.

But how can we read a "stale" variable if there are no new value yet? I mean the writing core will not write a new value until receiving Invalidation acknowledgedment from all the other cores.

Ritual

I think the claim about invalidation queues is that they can respond to the invalidate request before fully processing it, allowing in-flight loads to that line to still complete. I've never been clear on whether that's a relevant part of a hardware memory model or not, whether it's required to explain some possible reorderings that couldn't happen via other mechanisms. (i.e. whether it's just an implementation detail if it's a real thing at all.) I don't really understand it myself, but if it's important anywhere, I'd guess maybe a weak and complex model like PowerPC. – Increscent

Thank you for your answer, Peter. I guess there is some mystery on this topic.. I've not found proof if this is a case yet – Ritual

@PeterCordes, have you read this article? raw.githubusercontent.com/tpn/pdfs/master/…. There's 4.1 Invalidate Queues chapter which covers this problem. – Ritual

I think reading the "stale" value here means that the processor can read the cache line even though there is an invalidation for this cache in their invalidation queue (IQ). This is fine by cache coherence, and the writing core can go ahead and write a new value. Think of it to be similar to the case where the invalidation came after the read(s). Consider P1, P2, A=0 at t=0. P1 does rd A; A=1; rd A; P2 does rd A; rd A. It is fine for P1 to read (0, 1) and P2 to read either of (0,0,) or (0,1) or (1,1) based on when P2 executes its program and applies the invalidation for A=1 on P1. – Whallon