I would like to implement a ring buffer for convolution stuff in VHDL and make it generic. My problem is how to initialize the internal data without introducing further signals or variables.
Usually I can intialize the std_logic_vector by
signal initialized_vector : std_logic_vector(15 downto 0) := (others => '0');
But I have no clue how to do that onto an array by default.
Here's my code:
entity convolution_ringbuffer is
generic (
BitDepth_signal : integer := 24;
BufferSize : integer := 10
);
port (
data_in : in std_logic_vector(BitDepth_signal-1 downto 0);
sclk : in std_logic;
enable : in std_logic;
data_out : out std_logic_vector(BitDepth_signal-1 downto 0)
);
end convolution_ringbuffer;
architecture behavioral of convolution_ringbuffer is
type internal_data is array(0 to BufferSize-1) of std_logic_vector(BitDepth_signal-1 downto 0);
signal data_internal : internal_data;
begin
process ( sclk )
variable current_position : integer range 0 to (BufferSize-1) := 0;
begin
if ( rising_edge(sclk) and enable = '1' ) then
data_internal(current_position) <= std_logic_vector(data_in);
if ( current_position < BufferSize-1 ) then
current_position := current_position + 1;
else
current_position := 0;
end if;
end if;
if ( falling_edge(sclk) ) then
data_out <= std_logic_vector(data_internal(current_position));
end if;
end process;
end behavioral;