Convert enum type to std_logic_vector VHDL

Question

I want to know if it is possible to convert a enum type, like FSM states to std_logic_vector or integer. I'm doing a testbench with OSVVM for a FSM and I want to use the scoreboard package to automatically compare the expected state with the actual one.

Thanks!

Usher

Best and cleanest way is to implement a function with the enum input and with a return type of std_logic_vector (or integer) and use a case construct to return the correct std_logic_vector for its enum counterpart. – Stalk

But if the number of states increases, function increases too. I need something more portable... – Usher

See also attribute enum_encoding – Armoury

Answer 1

To convert to integer, use:

IntVal := StateType'POS(State) ; 

From there, it is easy to convert to std_logic_vector, but I prefer to work with integers when possible as they are smaller in storage than std_logic_vector. For verification, it will be easier if you start to think more about integers when the value is less than 32 bits.

If you need it as std_logic_vector, using only numeric_std you can:

Slv8Val := std_logic_vector(to_unsigned(IntVal, Slv8Val'length)) ; 

For verification, I liberally use numeric_std_unsigned, so the conversion is a easier:

Slv8Val := to_slv(IntVal, Slv8Val'length) ; 

In the event you have an integer and want to convert it back to a enumerated value, you can use 'VAL.

State := StateType'VAL(IntVal) ; 

In OSVVM, we use records with resolved values to create a transaction interface. We have a resolved types for integers (osvvm.ResolutionPkg.integer_max). We transfer enumerated values through the record using 'POS (as we put it in) and 'VAL (as we get it out).

Note don't confuse 'VAL with 'VALUE. 'VALUE converts a string to a value - opposite to 'IMAGE.

You of course learn all of this in SynthWorks' OSVVM class :).

Appoggiatura

Is there a similar way to go from the integer back to the enumerated type? – Diley

@Diley it is 'VAL (but I suspect you already knew this). Example edited in to the above. – Appoggiatura

What do you mean by "but I prefer to work with integers when possible as they are smaller in storage than std_logic_vector"? @JimLewis – Quartic

@Quartic Integers only have 0's and 1' and are stored in a single word in your computer - assuming that it is at least a 32 bit platform. Std_logic_vector on the other hand is based on std_ulogic which has 9 values: U, X, 0, 1, Z, W, L, H, -. To store one bit of Std_logic_vector requires at least 4 bits of memory. Hence, it requires more storage. – Appoggiatura

@JimLewis But you mean storage in the computer right? Not in FPGA. – Quartic

@Quartic Yes. Storage on the computer and not the FPGA - and good point on that. The impact is simulation run time and not FPGA. – Appoggiatura

Answer 2

Maybe like this...

function my_func(inp : t_my_enum) return integer is
begin
    case inp is
        when stateA =>
            return 1;
        when stateB =>
            return 2;
        when others =>
            return 0;
    end case;
end function my_func;

... <= my_func(stateB);`

Stalk