vhdl - 4 - McMap

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How to write an integer to stdout as hexadecimal in VHDL?

I can print an integer as decimal to stdout with: library std; use std.textio.all; entity min is end min; architecture behav of min is begin process is variable my_line : line; begin write(m...

vhdl ghdl

Clapperclaw asked 17/6, 2016 at 11:2

2

Solved

What's the general procedure for compiling an HDL Program for an FPGA?

I have a question regarding the compilation of HDL programs within the context of FPGA design. 1) Why does the compilation process take so long? Is it really the compilation process that takes a ...

vhdl verilog fpga system-verilog hdl

Outrank asked 4/5, 2016 at 23:11

1

Solved

Is the use of rising_edge on non-clock signal bad practice? Are there alternatives?

I am working on a VHDL design and I have it working, but the code is pretty ugly and the fact that it seems that I am trying to work around the language's design to accomplish my goal makes me feel...

syntax vhdl clock

Triode asked 4/5, 2016 at 18:37

2

Solved

vsim does not accept -modelsimini parameter on Windows

I'm using the command line argument -modelsimini <modelsim.ini> to specify my own modelsim.ini file for most QuestaSim / ModelSim executables. This works perfectly fine on Linux for vcom and...

vhdl modelsim questasim

Siler asked 3/5, 2016 at 23:26

1

Array of STD_LOGIC_VECTOR

I want to create an array that can hold std_logic_vectors as its elements, but im not sure how to place the elements into the array. My code to create the array is the following: type ist_array i...

arrays vector vhdl

Moor asked 27/4, 2016 at 6:13

2

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Get attribute of a field from a VHDL record type

Consider the following VHDL record: type big_record_t is record field_a : unsigned(15 downto 0); field_b : unsigned(23 downto 0); end record; Is it possible to get attributes on the record fie...

attributes vhdl

Prud asked 15/4, 2016 at 9:17

3

Solved

Is there a way to use one testbench for different simulators if both simulators need their own packages to be used?

My testbench uses a function that is defined in a modelsim package (init_signal_spy). So I can't use this testbench with a different simulator than ModelSims vsim, for example Candence's ncsim. But...

vhdl modelsim cadence

Bodywork asked 3/7, 2014 at 9:3

3

Solved

Component Instantiation vs Entity Instantiation in VHDL

I have experience with Verilog/SystemVerilog but I am new to VHDL and I am trying to figure out when I should use component instantiation or entity instantiation. By component instantiation I mean ...

vhdl

Belew asked 25/3, 2016 at 22:55

2

Solved

How can I see a variable's value for debugging VHDL code in modelsim?

I want to see a variable's value for debugging my code. But, I can see only signals and input and outputs value when I put mouse pointer on them, like in this picture (state is a signal here): B...

vhdl

Edwardedwardian asked 11/3, 2016 at 16:11

2

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Procedure call in loop with non-static signal name

In some testbench code I use a procedure to do something with a signal. I then use this procedure multiple times in sequence on different signals. This works fine as long as I explicitly define the...

vhdl modelsim

Fey asked 25/6, 2015 at 8:25

4

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VHDL difference between => and <=

I keep forgetting and its difficult to search for the answer in a textbook or the Internet.

syntax vhdl

Disability asked 2/11, 2011 at 22:29

4

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How to stop a simulation by timeout?

I have manageg to implement a simulation timeout in VHDL. If processes are running longer the MaxRuntime they get 'killed'. Unfortunately, this does not work the other way around. If my simulation...

vhdl simulation

Osgood asked 9/2, 2016 at 21:5

1

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Running multiple testbenches for VHDL designs

Whenever I create a VHDL design I tend to have many modules. Each of these modules are then connected to one main file and so everything is synthesised. But I want to write seperate test benches fo...

unit-testing vhdl verification ghdl test-bench

Brendabrendan asked 23/1, 2016 at 23:10

1

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Quartus II use file only in simulation

I want to run a simulation in Quartus. So I assign a Testbench in the Assignment menu. My testbench includes my DUT(D) and a extra component(E), which is only for simulation (so this component incl...

vhdl modelsim quartus

Dishwater asked 16/1, 2016 at 16:36

7

Solved

Creating a VHDL backend for LLVM?

LLVM is very modular and allows you to fairly easily define new backends. However most of the documentation/tutorials on creating an LLVM backend focus on adding a new processor instruction set and...

llvm vhdl

Secundine asked 8/9, 2010 at 4:44

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Calculating the Overflow Flag in an ALU

First of all, forgive me if this isn't the right place to post this question, but I wasn't sure where it should go. I am currently working on simulating an ALU in Xilinx with VHDL. The ALU has the ...

logic vhdl cpu

Bonnett asked 30/12, 2015 at 17:34

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Professional VHDL IDE? [closed]

Is there a good IDE to work with VHDL projects ? Or are most of the professionals working with emacs/vim/notepad++ ?

ide vhdl

Untouchability asked 20/5, 2010 at 12:15

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Finding the next in round-robin scheduling by bit twiddling

Consider the following problem. You have a bit-string that represents the current scheduled slave in one-hot encoding. For example, "00000100" (with the leftmost bit being #7 and rightmost #0) mean...

algorithm bit-manipulation verilog vhdl

Dryad asked 26/1, 2009 at 16:31

3

Why not a two-process state machine in VHDL?

When I learnt how to express finite state machines in VHDL, it was with a two-process architecture. One process handles the clock/reset signals, and another handles the combinatorial logic of updat...

vhdl idioms fsm

Vallecula asked 15/11, 2015 at 10:26

3

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VHDL multiple std_logic_vector to one large std_logic_vector

I have four std_logic_vectors (15 downto 0) and want to stack them into a std_logic_vector (63 downt 0) so fare I have found one way of doing it but is it the correct way or is there a more optimal...

vhdl

Remmer asked 14/10, 2015 at 15:55

4

Solved

Verilog/VHDL - How to avoid resetting data registers within a single always block?

I like to avoid resetting data registers that don't need to be reset. For example, when streaming data through pipeline stages, if each stage has a valid bit, there is no need to reset the data reg...

asynchronous vhdl verilog reset synchronous

Sere asked 31/1, 2014 at 0:39

1

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Variable number of inputs and outputs in VHDL

I should create an entity in VHDL that has a variable number of inputs and outputs. This number of pins should be given from the GENERIC construct. Let's suppose to have this code: entity HELLO is...

generics vhdl

Kraut asked 14/9, 2015 at 10:25

2

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Testing FPGA Designs at Different Levels

Various aspects of test strategies for FPGAs have been discussed here on SO but I can't find that the following question has been asked/discussed/answered: At what levels should you simulate your ...

testing vhdl verilog fpga

Radiopaque asked 3/9, 2015 at 17:5

3

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Signals and ports on which side of the "arrow" =>

How do I know where the port/signal/value should be placed on which side of the arrows? I noticed that by switching port_a => x to x <= port_a which seems very equal, I got an error. Also, x ...

vhdl

Bailly asked 18/4, 2012 at 9:40

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What is the practical difference between implementing FOR-LOOP and FOR-GENERATE? When is it better to use one over the other?

Let's suppose I have to test different bits on an std_logic_vector. would it be better to implement one single process, that for-loops for each bit or to instantiate 'n' processes using for-generat...

for-loop vhdl fpga hardware asic

Alvey asked 13/7, 2015 at 21:16

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