I'm using Ubuntu Linux 14.04 LTS with Altera Quartus 15.0 web-edition and I'm having a hard time simulate my design due to licensing errors. I'm designing an LCD_driver for the VEEK-MT's LCD touch ...

I've looked at all the previous questions and no one seems to have a problem as simple as mine. Also I've searched the web and can't find a solution. I'm new to VHDL and am trying to compile the si...

I have recently moved to Linux and am getting used to the OS, I managed to install and run Quartus 20.1 Lite and I was testing it out with an old working project. When I opened my waveform and ran ...

What are .rbf files and how can i generate them from the Quartus output file .sof on windows ?

I'm using Altera Quartus 2 to do a custom 8 bit processor and it takes forever to compile on my laptop. I'm only using simulations and making my processor in schematic (block diagram) and VHDL. Rig...

I want to run a simulation in Quartus. So I assign a Testbench in the Assignment menu. My testbench includes my DUT(D) and a extra component(E), which is only for simulation (so this component incl...

Installed Quartus 13.0 with Modelsim in Fedora 22 64-bit. Running Quartus in 32-bit because I get lots and lots of problems otherwise. However, I can start Quartus, create a project, synthesize it,...

I have the following VHDL code, its a entity of a project: library ieee; use ieee.std_logic_1164.all; library work; use work.typedef.all; entity uc is port(faaaa: in std_logic_vector(15 downto 0...