RISCV instructions

Question

I am new to riscv and I am confused between la and lw.

I know that la stands for load address and lw stands for load word. If address of VAL is 0x100 and data value of VAL is 0x11 should x3 stores 0x100 and x4 stores 0x11?

la x7, VAL
sw  x3, 0(x7)
lw  x4, VAL
bne x4, x3

Serration

Answer 1

la t0, SYMBOL is an assembler pesudo instruction that puts the address of SYMBOL into t0. Depending on the addressing mode, it expands to something like

lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]

where SYMBOL[31:12] is the high bits of SYMBOL, and SYMBOL[11:0] is the low bits of SYMBOL -- these aren't valid assembler syntax, and there's some tricks to play with sign extension to get this exactly correct.

lw t0, SYMBOL is an assembler pseudo instruction that puts the value of memory at the address SYMBOL into t0. Depending on the addressing mode, it expands to something like

lui t0, SYMBOL[31:12]
lw  t0, SYMBOL[11:0](t0)

Specifically the difference is that lw performs a load from memory, while la just generates an address. The sequence

la t0, SYMBOL
lw t0, 0(t0) # load word from memory address 0(t0)

is functionally equivalent to

lw t0, SYMBOL

but takes an extra instruction, specifically

lui t0, SYMBOL[31:12]
addi t0, t0, SYMBOL[11:0]
lw t0, 0(t0)

vs

lui t0, SYMBOL[31:12]
lw t0, SYMBOL[11:0](t0)

This should all be documentation in the RISC-V Assembly Programmer's Manual, but that is always a work in progress. If you find that's lacking then feel free to submit a patch or open an issue.

Greenhead

Answer 2

la computes an pointer-sized effective address, but does not perform any memory access.  The effective address itself is what is loaded into x7.

(Also note that la is a pseudo instruction that may expand into two instructions, depending on VAL — none the less, the sequence computes an effective address and that is its result (no memory access is performed).)

lw also computes an effective address; however, it uses the effective address in a word-sized memory access, and the result of that memory access is the value loaded into x4.

lb would do the same as lw except that the memory access is byte-sized.

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As far as your code sequence goes, the value that was in x3 (which cannot be determined from your code snippet) will be stored into memory at locations 0x100-0x103 (this is a word-sized store).

The lw will reload the value that was written by the sw.  (Note that the lw in this case may also expand to multiple instructions depending on VAL, whereas the sw is a single instruction regardless of VAL.)

The bne (though missing a target label) will not branch.

Ludwick

Answer 3

la instruction is a pseudoinstruction, it gets the address of the symbol. In specifications, it means:

From: Specifications Volume 1, Unprivileged Spec v. 20191213 (https://riscv.org/technical/specifications/)

The la will be different according the symbol:

1. When the symbol in la is non-PIC(non Position Independent Code), the la will be resolved as auipc and addi.

2. When the symbol is PIC(Position Independent Code), the la will be resolved as auipc and l{w|d}. The symbol will be extend as GOT[symbol], the GOT means: Global Offset Table. And the RV32I use the lw, the RV64I use the ld.

The lw instruction loads a 32-bit value from memory into rd.

So, it is not only a simple 'address' vs 'value' problem, but also depends on the platform and symbol. Because the la will be resolved as different instructions on different situations.

Anthropologist