I have read that there are some registers that an x86 CPU cannot modify while in user mode (I believe these registers are called "privileged registers"). But can an x86 CPU read the values of thes...

I'm currently working on a homework problem that asks me to find out the number of machine code instructions that are executed when running a short program I wrote in C. The question says I am abl...

I have read through Intel's Software Development Guide's (vol 1-3). Without doing a doing a similar read through AMD's Programming Guides (vol 1-5), I am wondering what aspects of Intel and AMD's ...

Iam confused whether system calls and instruction set are synonymous? Do the instructions like MOV, LOAD, CALL, IN, OUT , ADD, SUB etc fall in the category of system calls? System call instructions...

The AVX instruction set introduced VPERMILPS which seems to be a simplified version of SHUFPS (for the case where both input registers are the same). For example, the following instruction: c5 f0...

ARM assembly has SWI and SVC instructions for entering into 'supervisor mode'. What confuses me is, why there are two of them? Here it is said that SVC was formerly SWI. Does it mean that basicall...

I have this risc v code : lui S0, 0x1234 ori S1, S0, 0x5678 add S2, S1, S1 and the question asks me, "What does the register S2 hold?" The question explains that lui and I quote: "L...

I learned about one address, two address, and three address instruction, but now I'd like to know, what kind of address instruction does x86 use?

The PREFETCHNTA instruction is basically used to bring the data from main memory to caches by the prefetcher, but instructions with the NT suffix are known to skip caches and avoid cache pollution....

The convolutional layers are most computationally intense parts of Convolutional neural networks (CNNs).Currently the common approach to impement convolutional layers is to expand the image into a ...

Where can I find data about "market share" of x86 microarchitectures? What percentage of users of x86-family CPUs have a CPU that supports SSE4.2, AVX, AVX2, etc.? I'm distributing precompiled bin...

Are there any still-relevant CPUs (Intel/AMD/Atom) which don't support SSSE3 instructions? What's the most recent CPU without SSSE3?

If you need to multiply two arbitrary signed numbers in MIPS, is there a reason to prefer: mul $t0 $s0 $s1 Or this: mult $s0 $s1 mflo $t0 ? I'm finding inconsistent answers online with regar...

I have written and cross compiled a small c++ program, and I could run it in an ARM or a PC. Since ARM and a PC have different instruction set architectures, I wanna to compare them. Is that possib...

Hi I was reading a textbook that compare conditional data transfers and conditional control transfers in assembly: above is the gotodiff (conditional jump) below is the cmovdiff (conditiona...

I am currently trying to understand the inner code of the glibc's syscall function. Below is the code (taken from here). /* In the EABI syscall interface, we don't need a special syscall to imple...

The Intel® 64 and IA-32 Software Developer's Manual, Volume 2A, Section 3.1.1.1 mentions the notation ct to denote a 10-byte value following the opcode. I am however unable to find any instruction ...

AFAIK x86-64 adds a number of general purpose registers to those derived from Intel x86 (rax, rcx, etc), called r8-r15. Why did they name the new registers like this? Why not just follow existing ...

Here's the instruction which copies (converts) unsigned registers: http://www.felixcloutier.com/x86/MOVZX.html Basically the instruction has 8->16, 8->32, 8->64, 16->32 and 16->64. Where's the 32...

I was working on the C++ implementation of Shamir's secret sharing scheme. I split the message into 8-bit chunks and on each performs corresponding arithmetic. The underlying finite field was Rijnd...

I have read different things about how a memory barrier works. For example, the user Johan's answer in this question says that a memory barrier is an instruction that the CPU executes. While the ...

I can understand how one can write a program that uses multiple processes or threads: fork() a new process and use IPC, or create multiple threads and use those sorts of communication mechanisms. ...

How does the xchg instruction work in the following code? It is given that arrayD is a DWORD array of 1,2,3. mov eax, arrayD ; eax=1 xchg eax, [arrayD+4] ; eax=2 arrayD=2,1,3 Why isn't the array 1...

I'm having a bit of trouble understanding the rlwinm PPC Assembly instruction (Rotate Left Word Immediate Then AND with Mask). I am trying to reverse this part of a function rlwinm r3, r3, 0, 28,...

I am confused about the difference between add and addu. The MIPS instruction reference says: add (with overflow) add unsigned (no overflow) My understanding is to use add with signed operands...