instruction-set Questions
1
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On Intel and AMD x86_64 processors, SIMD vectorized registers have specific fused-multiply-add capabilities, but general-purpose (scalar, integer) registers don't - you basically need to multiply, ...
Ambriz asked 13/3, 2018 at 10:35
3
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I'm designing a simple toy instruction set and accompanying emulator, and I'm trying to figure out what instructions to support. In the way of arithmetic, I currently have unsigned add, subtract, m...
Theological asked 31/1, 2014 at 8:16
0
From the intel instruction reference:
68 id PUSH imm32
It means pushing dword-sized immediates is valid in 64-bit program.
So I wrote the following program:
section .text
global _start...
Beanstalk asked 9/2, 2018 at 12:22
1
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So I'm looking into the source code for Redox OS (An operating system made with Rust) just to see if I can learn something.
I'm reading the assembly file start.s in the bootloader folder. In the i...
Auxesis asked 3/1, 2018 at 20:26
2
Solved
I have an assignment where, among other things, I need to look in an .asm file to find a certain instruction and "reverse engineer" (find out) what part of the C code causes it to be executed on an...
Solubility asked 18/12, 2017 at 10:8
5
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Does anyone know of a web site where I can find a list of 32-bit MIPS instructions/opcodes, with the following features:
Clearly distinguishes between real opcodes and assembly-language macros (ps...
Successive asked 25/9, 2008 at 20:38
1
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The Rijndael key schedule procedure involves RotWord, SubWord, and XOR, which are all supported by
_mm_aeskeygenassist_si128:
X3[31:0] ← SRC [127: 96];
X2[31:0] ← SRC [95: 64];
X1[31:0] ← SRC [63...
Adenitis asked 1/10, 2017 at 13:30
3
Solved
I am experiencing some difficulties interpreting this exercise;
What does exactly xorl does in this assembly snippet?
C Code:
int i = 0;
if (i>=55)
i++;
else
i--;
Assembly
xorl ____ , %e...
Rumanian asked 10/5, 2014 at 0:8
1
How does the CPU distinguish CALL rel16 (E8 cw) and CALL rel32 (E8 cd)?
According to this site, mirroring the Intel architecture manuals, the opcodes for CALL rel16 and CALL rel32 are E8 cw and E8...
Lundell asked 3/7, 2017 at 9:40
1
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There's this related question: GCC: how is march different from mtune?
However, the existing answers don't go much further than the GCC manual itself. At most, we get:
If you use -mtune, then t...
Parricide asked 12/6, 2017 at 1:42
1
While going through the RISC-V Specification I've noticed that the 64-bit version differs from the 32-bit one in the fact, that it
Widened the registers to 64-bit
Changed the instructions to act ...
Catalysis asked 6/3, 2017 at 13:50
1
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I would like to know how to know which instruction set my processor using; I am running Linux.
I would also like to understand how a processor can handle many instruction sets.
When I type cat /p...
Calderon asked 16/3, 2017 at 22:50
7
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I was wondering if instruction set and assembly language are the same thing?
If not, how do they differ and what are their relations?
Thanks and regards!
Burbank asked 21/3, 2011 at 18:44
3
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According to the documentation, there is a fma() function in math.h. That is very nice, and I know how FMA works and what to use it for. However, I am not so certain how this is implemented in prac...
Curb asked 20/2, 2015 at 14:5
1
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i'm tring to understand how can i max out the number of operations i can get on my CPU. I'm doing a simple matrix multiplication program, and i have a Skylake processor. I was looking at the wikipe...
Barberabarberry asked 7/1, 2017 at 23:53
1
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In the RISC MIPS instruction set, we have load byte (lbu), load half word (lhu) and load word (lw) instructions. It appears to me that everything lbu and lhu can do can be achieved with lw.
So wh...
Alboran asked 26/11, 2016 at 11:38
6
Solved
Do graphic cards have instruction sets of their own?
I assume they do, but I have been wondering if they are proprietary or if there is some sort of open standard.
Is every GPU instruction preceded...
Comorin asked 8/11, 2009 at 20:32
6
Solved
I am learning MIPS 32 bit. I wanted to ask that why do we Sign Extend the 16 bit offset (in Single Cycle Datapath) before sending it to the ALU in case of Store Word?
Wicklow asked 18/9, 2011 at 14:5
1
I want to get xor value of two register.But compile return error how to write XOR in assembly(ARM)
XOR r1,r1,r0;
compiler gives like error,
Error: bad instruction `xor r1,r1,r0'
Flatcar asked 25/7, 2016 at 20:59
1
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I know people have asked similar questions like this before, however there is so much conflicting information that I really want to try and clear it up once and for all. I will attempt to do so by ...
Kantian asked 22/7, 2016 at 1:27
4
Solved
In Intel architecture IA32, instructions like movl, movw does not allow operands that are both memory locations. For example, instruction movl (%eax), (%edx) is not permitted. Why?
Irfan asked 14/8, 2012 at 13:29
2
Solved
I have came across the concepts of link register and leaf functions recently.
I understand from previous SO reads that the LR tells where the code was previously during execution. I also got to kn...
Technicolor asked 29/6, 2016 at 12:28
2
Solved
Could someone explain to me why there are 3 variants of the fused multiply-accumulate instruction: vfmadd132pd, vfmadd231pd and vfmadd213pd, while there is only one C intrinsics _mm256_fmadd_pd?
T...
Galvanize asked 3/4, 2016 at 21:57
4
What does the following line do in arm assembly:
000031e6 2916 cmp r1, #22
000031e8 bf1a itte ne
I get the first line (comparing r1 to 22) but what about the second line (I've never seen the itt...
Riviera asked 12/8, 2011 at 15:17
4
I am bit confused with instruction size and addressable space (I assumed that instruction size should be same as size of address bits. I did not find enough explanation in my book)If I am correct, ...
Alvaroalveolar asked 20/11, 2015 at 15:38
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