instruction-set Questions
4
Solved
I first came across the ARM instruction set in the 80's, and have not used it since. Out of curiosity I was looking at the the tablets and other ARM devices and note that the CPU's are produced by ...
Melvin asked 12/1, 2012 at 3:35
3
Solved
In the RISC-V Instruction Set Manual, User-Level ISA, I couldn't understand section 2.3 Immediate Encoding Variants page 11.
There is four types of instruction formats R, I, S, and U, then there i...
Sangfroid asked 10/9, 2016 at 14:35
2
Solved
We know that jal specifies a 21-bit offset. However, it does not encode a 21-bit offset but a 20-bit one. The reason is that the least significant bit of an address is always zero because the small...
Ladyfinger asked 25/12, 2019 at 18:12
3
Solved
recently i checked the Instruction Set for an ARM Cortex-M3 processor.
For example:
ADD <Rd>, <Rn>, <Rm>
What do those abbriviations mean exactly?
I guess they mean different ...
Sextuplicate asked 15/1, 2016 at 19:31
2
First I am a little bit confused with the differences between movq and movabsq, my text book says:
The regular movq instruction can only have immediate source operands that can be represented as 32...
Millet asked 7/7, 2020 at 8:42
12
Solved
I would like to know what the difference between these instructions is:
MOV AX, [TABLE-ADDR]
and
LEA AX, [TABLE-ADDR]
Unbated asked 9/11, 2009 at 8:32
2
Solved
I notice that Intel Tremont has 64 bytes store instructions with MOVDIRI and MOVDIR64B.
Those guarantees atomic write to memory, whereas don't guarantee the load atomicity. Moreover, the write is w...
Petronia asked 28/2, 2019 at 5:57
1
Solved
The orpd instruction is a "bitwise logical OR of packed double precision floating point values". Doesn't this do exactly the same thing as por ("bitwise logical OR")? If so, what's the point of hav...
Weka asked 31/5, 2020 at 5:28
1
Solved
It it safe to assume that x64 builds can use TZCNT without checking its support through cpu flags?
Turbot asked 25/4, 2020 at 8:18
1
Solved
I need to disable all AVX512 extensions in gcc-compiled code. The reason is that Valgrind chokes on AVX512 instructions. Is there a way to do it with a single flag?
I know how to disable each ext...
Glindaglinka asked 23/3, 2020 at 14:17
1
Solved
In the RISC-V Unpriviliged spec V20191213, the following is stated, (page 21)
The unconditional jump instructions all use PC-relative addressing to help support position-independent
code.
Loo...
Nit asked 20/3, 2020 at 14:54
4
Solved
A very common pattern in programming is to cap a value at a maximum after some kind of update. What I'd like to know, is if there's a difference between the following two pieces of code, and if one...
Shaw asked 21/3, 2013 at 5:34
4
I'm trying to understand the instruction sets of old microcontrollers, especially the 6502.
The documentation of the instruction set that can be found here lists two shift instructions (beside the...
Ileum asked 25/1, 2019 at 2:45
4
Solved
In the MIPS ISA, there's a zero register ($r0) which always gives a value of zero. This allows the processor to:
Any instruction which produces result that is to be discarded can direct its target...
Vociferate asked 9/7, 2014 at 5:41
2
I am reading a book "Computer Organization and Design RISC-V Edition", and I came across the encoding for S-B and U-J instruction types.
Those types I have mentioned above has strange encoded imme...
Lasonde asked 16/10, 2019 at 13:40
1
Solved
I've looked everywhere and I still can't figure it out. I know of two associations you can make with streams:
Wrappers for backing data stores meant as an abstraction layer between consumers and ...
Nonpros asked 4/11, 2019 at 20:17
1
Solved
So I am learning how x86 works and have come across people saying that it is byte-addressable, yet can read words, double words, etc.
How does the processor decide which method to use and when?
E.g...
Allness asked 30/10, 2019 at 14:56
9
Solved
Are assembly language and machine language (for the same underlying system) really the same? Are there any differences between these two concepts?
Gaylenegayler asked 10/8, 2009 at 5:50
3
Solved
I am reading about x86-64 (and assembly in general) through the book "computer systems a programmer's perspective"(3rd edition). The author, in compliance with other sources from the web, states th...
Sugihara asked 18/9, 2019 at 18:38
1
Solved
I'd like to ask if using a CMPXCHG instruction on an 8-bit memory field would be worse in any aspect than using it on a 32-bit field.
I'm using C11 stdatomic.h to implement a couple of synchroniza...
Dilatory asked 3/10, 2019 at 7:8
1
why two separate instructions instead of one instruction? Practically in what kind of situations we need to use CMP and TEQ instructions.
I know how both the instruction works.
Curse asked 4/9, 2019 at 11:28
2
Solved
I'm reading the book The RISC-V Reader: An Open Architecture Atlas. The authors, to explain the isolation of an ISA (Instruction Set Architecture) from a particular implementation (i.e., microarchi...
Uproot asked 23/7, 2019 at 19:48
3
Solved
I want to test some architecture changes on an already existing architecture (x86) using simulators. However to properly test them and run benchmarks, I might have to make some changes to the instr...
Muslin asked 7/11, 2013 at 12:44
3
Are there any RISC architectures which allow arithmetic operations to be applied individually to bytes, half-words and other data cells, whose size is less than the size of the CPU general purpose ...
Bouzoun asked 6/12, 2017 at 4:37
1
Solved
I've got an application that requires AVX2 to work correctly. A check was implemented to check during application start if CPU has AVX2 instruction. I would like to check if it works correctly, but...
Wallacewallach asked 19/4, 2019 at 13:7
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