mmu Questions
11
Solved
I am reading Operating Systems Concept and I am on the 8th chapter! However I could use some clarification, or reassurance that my understanding is correct.
Logical Addresses: Logical addresses a...
Whensoever asked 13/9, 2010 at 3:43
2
Solved
In the book "Low-Level Programming: C, Assembly, and Program Execution on Intel® 64 Architecture" I read:
Each virtual 64-bit address (e.g., ones we are using in our programs)
consists o...
Antilog asked 1/10, 2017 at 4:17
1
I've researched on the topic for disabling of write protection on kernel text on linux, and I can only find solutions for x86 linux, which is temporarily clearing bit 16 of the cr0 register, write ...
Rarebit asked 27/7, 2015 at 8:19
1
Solved
I'm trying to understand how the Zircon's (Fuchsia OS kernel) allocs page in ARM64, so I found mmu.cpp https://fuchsia.googlesource.com/fuchsia/+/4277d3203daa0fc5e4dd1625cf96891dd9882f44/zircon/ker...
1
In a systems memory map (also called cpu memory map) the address ranges are allocated for RAM memory ranges, MMIO for PCI devices etc.
Lets take an example where address ranges for RAM is started...
Vaunting asked 10/9, 2018 at 8:35
7
Solved
On a single core computer, one thread is executing at a time. On each context switch the scheduler checks if the new thread to schedule is in the same process than the previous one. If so, nothing ...
Utrillo asked 29/3, 2012 at 16:46
2
Solved
What is the role of memory controllers and how are they different from the MMU inside the processor? is it that the MMU job is to translate virtual addresses to physical ones (among other things) a...
Erleena asked 8/4, 2014 at 0:34
3
My understanding currently is,
I can write an operating system in C
I can write a program for that operating system in C
When I write an operating system I can see all of the memory
When I write...
Ammonic asked 17/11, 2019 at 1:15
1
Solved
In Linux user space: suppose that I allocated a 3MiB continuous memory ABC, where A, B and C are 1MiB each. Is there a way to access AC as a single continuous 2MiB memory somehow (a kind of user sp...
1
Solved
To my knowledge, both MMU and TLB are not shared in a hyper-threaded core in Intel x86_64.
However, then, if two threads that don't share the address space are scheduled to the same physical core,...
Serow asked 16/7, 2018 at 11:31
1
Solved
I just want to clarify the concept and could find detail enough answers which can throw some light upon how everything actually works out in the hardware. Please provide any relevant details.
In c...
Gan asked 29/9, 2017 at 0:16
1
Solved
1
Solved
Usually, lists are implemented either as linked lists, which are slow to traverse, or as array lists, which are slow when inserting elements.
I was wondering if it would be possible to use the pro...
Unhinge asked 6/1, 2017 at 3:23
1
Solved
When I debug MMU in Cortex-A9 MPCore, I always see Domain Access Control Register, but, what does domain means ? up to 16 domains ?
Anyone can give me a link to explain this ?
3
Solved
I'm trying to understand how unaligned memory access (UMA) works on modern processors (namely x86-64 and ARM architectures). I get that I might run into problems with UMA ranging from performance d...
Sihon asked 11/5, 2014 at 14:46
2
Solved
I was trying to see memory map of a process on Linux x86-64 using pmap -x command. I got confused looking at the output of the pmap. Particularly for the entries for mapping dynamic libraries. Ther...
Spondaic asked 22/3, 2012 at 19:2
3
Solved
It seems (from looking at the Linux kernel source) that the Swap: metric in /proc/pid/smaps is the total swap accessible by the given pid.
In the case where there is shared memory involved, this s...
2
Solved
Does anybody know if TLBs (L1 and L2) support simultaneous accesses with multiple page sizes in modern x86_64 microprocessor (Intel SandyBridge, AMD Bulldozer)? Does x86 core pipeline provides info...
1
I am little confused about how linux takes advantage of ARMv7 MMU hardware for its 3 level page table walk. MMU has only 2 registers ttbr0 and ttbr1 (one for kernel and other for user-space). How d...
2
I feel confuse in page table management in Linux kernel ?
In Linux kernel space, before page table is turned on. Kernel will run in virtual memory with 1-1 mapping mechanism. After page table is t...
Exemplum asked 22/5, 2013 at 9:42
2
Solved
I want to write my code that will handle TLB misses on the Microblaze and through that, of course, the page tables etc. This is all being done on OVPsim.
As I am learning as I go I wrote this litt...
Veg asked 17/11, 2014 at 23:20
3
Solved
I have the following specifications of an ARM based SoC:
L1 Data cache = 32 KB, 64 B/line, 2-WAY, LRU
L2 Cache = 1 MB, 64 B/line, 16-WAY
L1 Data TLB (for loads): 32 entries, fully associative
L2 ...
Lehmbruck asked 15/11, 2014 at 11:44
1
Solved
I have a question about relationship between linux kernel and MMU.
I now got a point that the linux kernel manages page table between virtual memory addresses and physical memory addresses.
At the ...
Phonologist asked 24/9, 2014 at 11:59
1
Solved
Consider the following situation: the kernel has exhausted the physical RAM and needs to swap out a page. It picks least recently used page frame and wants to swap its contents out to the disk and ...
Diploblastic asked 15/5, 2013 at 9:15
1
Solved
I enabled MMU on my s3c2440 board (3G - 4G memory :: the fault attribute),everything was just fine when I didn't read/write 3G - 4G memory .So to test the page fault vector ,I wrote to a 0xFF to th...
1 Next >
© 2022 - 2024 — McMap. All rights reserved.