ARM MMU and ARM Linux page table walk

Question

I am little confused about how linux takes advantage of ARMv7 MMU hardware for its 3 level page table walk. MMU has only 2 registers ttbr0 and ttbr1 (one for kernel and other for user-space). How does mmu know know multi-level page table walk of linux?

Thanks, Hvr

Elytron

A software page table walk works exactly the same way as a hardware page table walk - given a base address, look up the relevant entry and decode it to either a fault, a mapping, or the address of the next-level table (and repeat). You do know how multi-level page tables work in general, right? – Beneath

I do not fully understand it. What I mean is to do software page table walk, isn't it too much for each fetch/load? Shouldn't it be done by hardware only? I have tried to read many links but could not fully understand it. Can you provide some meaningful links for understanding this topic? – Elytron

Answer 1

If the upper N bits of the virtual address are all zero then the translation starts at TTBR0 else TTBR1. N comes from the TTBCR. The TTBRn registers contain the physical address of the base of the first-level table. The appropriate entry of the first-level table is loaded and various bits of the entry determine if the translation uses a second-level table and if so what its physical address is.

The MMU can be configured to use Short Descriptors (32-bit physical addresses) or Long Descriptors (40-bit physical addresses). When using short descriptors, at most only two-levels of translation table can be used. When using long descriptors, there can be three levels.

This ignores stage 2 translations (Hypervisors). All is documented in the ARMARM for v7-A&R section B3.3: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0406c/index.html

Dealfish