how is CPU physical address space mapped to physical DRAM?

Question

In a systems memory map (also called cpu memory map) the address ranges are allocated for RAM memory ranges, MMIO for PCI devices etc.

Lets take an example where address ranges for RAM is started from address 0 to upto 512MB which includes DOS compatibility memory space starts from 0 and goes upto 1MB.

Now when we say that this 512MB of region will be mapped into the memory, does this mean that the address 0 in the CPU address space will be mapped to address 0 in the Physical RAM and the same goes up to 512MB? If not then how the mapping is done?

Also does the memory address ranges allocated in CPU address space will be exactly equal to the size of the RAM installed in the system? If its not the case then how the mapping would take place in such case?

Also how will memory mapping of DOS compatibility region be done? Does this region will be unused into the memory if using an OS other than DOS?

Also does the memory mapping means that when the CPU generates the address from 0 to 512 MB only will be redirected into the RAM ? Any other address generated by CPU will never be directed into the RAM by MMU ? In such case all the application would have the address between ranges from 0 to 512MB inorder to access the Memory ?

I'm considering an x86 system here.

Vaunting

The real world is a bit more complex. Think about memory mapped files, mapped IO-space for special drivers, remapping for DMA if system did not support DMA on all address ranges. And it seems that you have missed virtual mememory ( swap space ) in general.# – Fumigant

Your question requires writing a whole book to answer. The process of mapping physical addresses to DRAM addresses in modern processors is undocumented and complicated. It's undocumented to make rowhammer attacks more difficult. But it can certainly be reverse-engineered. – Vestment

Related: X86 Address Space Controller? – Dippy

This question is very broad, and contains several questions as well. This is not a site for please write me a book about this topic. Spend some time with Google doing some research yourself; this is all explained very well on many other sites. – Elconin

Answer 1

Before going into the question, it's worth taking a look into DRAM architecture.

Now when we say that this 512MB of region will be mapped into the memory, does this mean that the address 0 in the CPU address space will be mapped to address 0 in the Physical RAM and the same goes up to 512MB? If not then how the mapping is done?

There isn't exactly a concept of 'address 0' in DRAM, instead, there is an architecture of channels, DIMM, ranks, chips, banks, rows and columns, and the DRAM controller generates 'commands' that activates parts of the DRAM and selects data from the cells:

So the answer to the first question is no. As other people mentioned, the exact mapping is complicated and undocumented. If you are interested, AMD does provide documentation (Section 2.10 and 3.5), and there are attempts of reverse engineering Intel's mapping (Section 4).

Also does the memory address ranges allocated in CPU address space will be exactly equal to the size of the RAM installed in the system? If its not the case then how the mapping would take place in such case?

The answer is also no for many reasons. You answered one of them: the physical address space represents more than just RAM/memory, there are also PCIe devices, ROM (where BIOS is located), etc, and thus there are memory holes. To inspect what does the physical address correspond to in the system, in Linux take a look at /proc/iomem, as it has the mappings.

Also how will memory mapping of DOS compatibility region be done? Does this region will be unused into the memory if using an OS other than DOS?

Yes, I believe these are unused memory holes.

Also does the memory mapping means that when the CPU generates the address from 0 to 512 MB only will be redirected into the RAM ? Any other address generated by CPU will never be directed into the RAM by MMU ? In such case all the application would have the address between ranges from 0 to 512MB inorder to access the Memory ?

MMU serves a completely different purpose. Take a look at virtual address to physical address translation.

Seasonseasonable