I have a test bench that monitors a bus. Some of the signals (bits) within the bus can be 1'bx. For a variety of reasons, I need to know if any of the signals within the bus are 1'bx. What's the be...

Whenever I create a VHDL design I tend to have many modules. Each of these modules are then connected to one main file and so everything is synthesised. But I want to write seperate test benches fo...