Running multiple testbenches for VHDL designs

Question

Whenever I create a VHDL design I tend to have many modules. Each of these modules are then connected to one main file and so everything is synthesised. But I want to write seperate test benches for each of these modules and one for the global process. It would be nice if I could do something to link all of these testbenches together and make them run in succession, to test my entire design in one run. How could I do this? I like to use GHDL and asserts. Is it possible to create one super-testbench? Or would a shell script which iterates over them be better?

Brendabrendan

Good strategy. There are unit testing tools for VHDL too ... one called VUnit for example : github.com/LarsAsplund/vunit – Hoo

@Paebbels, you are right. Fixed. – Brendabrendan

Answer 1

The short answer is VUnit.

It's officially supported by the open source VHDL simulator GHDL and comes also with OSVVM - a set of testbench helper packages for random value generation and test coverage.

You should considder using GHDL 0.34dev (build from sources), because it got some fixes for vunit and OSVVM.

All sources are available in GitHub repos:

• GHDL -> https://github.com/ghdl/ghdl
• VUnit -> https://github.com/VUnit/vunit
• OSVVM -> https://github.com/OSVVM/OSVVM

Balinese