What do the abbriviations (Rn, Rd, ...) in the instruction set of ARM mean?

Question

recently i checked the Instruction Set for an ARM Cortex-M3 processor. For example:

ADD <Rd>, <Rn>, <Rm>

What do those abbriviations mean exactly? I guess they mean different kinds of addresses, like directely addressed, relatively addressed or so. But what exactly?

Thanks!

Sextuplicate

the key is to connect the dots, you see the ascii/asm representation of the instruction then you see the machine code binary definition so you can see which bits go where. they could have just as easily said ra, rb, rc...as already answered d likely means destination. n and m? – Sthenic

Answer 1

Basics:

• Rd is the destination, Rn and Rm are sources. They're all general-purpose integer registers; FP would use Sd / Sn / Sm or Dd / Dn / Dm for single or double.
  ARM syntax puts the destination(s) on the left, before read-only source operands.

See Notlikethat's answer for more. Some small additions to that:

• t: in this post, an ARM employee comments that "t" might mean "transfer" instead of "target".

  Since t generally appears in memory instructions like LDR and STR, I understand that that means "transfer to/from memory", e.g. on ARMARMv8-fa:

  LDR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
  STR <Xt>, [<Xn|SP>, (<Wm>|<Xm>){, <extend> {<amount>}}]
  

  where the t is the source/destination of memory reads and writes.

  This is also further suggested in the description of the STR and LDXR instruction registers:

  <Xt> Is the 64-bit name of the general-purpose register to be transferred, encoded in the "Rt" field.

  The LDR instruction however says "loaded":

  <Xt> Is the 64-bit name of the general-purpose register to be loaded, encoded in the "Rt" field.

  This terminology is especially meaningful because ARM is RISC-y and so there are relatively few instructions that do memory IO, and they tend to do just that (unlike say add and store to memory as is common in x86).

• t1 and t2: these are used for memory instructions that load/store two values at once, e.g. the ARMv8 LDP/STP:

  LDP <Xt1>, <Xt2>, [<Xn|SP>], #<imm>
  STP <Xt1>, <Xt2>, [<Xn|SP>, #<imm>]!
  

• n and m are just commonly used integer variable/index names in mathematics

• s:

  • the STXR instruction stores to memory fom Xt (like STR), but it also gets a second return value (did the write succeed) to Ws:

    STXR <Ws>, <Xt>, [<Xn|SP>{,#0}]
    

    so presumably s was chosen because it comes before t like m comes before n.

  • Some ARMv7/aarch32 instructions could take a shift in a register, and Rs is the name given to that register, e.g.:

    ORR{<c>}{<q>} {<Rd>,} <Rn>, <Rm>, <shift> <Rs> 
    

    I couldn't easily find aarch64 ones.

• if it were documented, "Chapter C2 About the A64 Instruction Descriptions" might have been a good location for the information, but it's not there

Ketch

Answer 2

Operands of the form <Rx> refer to general-purpose registers, i.e. r0-r15 (or accepted aliases like sp, pc, etc.).

I'm not sure if it's ever called out specifically anywhere but there is a general pattern of "d" meaning destination, "t" meaning target, "n" meaning the first operand or base register, "m" meaning the second operand, and occasionally "a" meaning an accumulator. Hence why you might spot designations like <Rdn> (in the destructive two-operand instructions), or <Rt>, <Rt2> (where a 64-bit value is held across a pair of GP registers). This is consistent across the other types of register too, e.g. VADD.F32 <Sd>, <Sn>, <Sm>.

Sanguineous

Answer 3

They are just there to define registers, the lowercase letter just being there to separate them for explanation. Rd is destination, but Rn, Rm etc are just any register you can use. It's the only way to tell which is which when explaining like "Rd equals Rn bitwise anded with Rm", for example, since you can't use numbers.

They could be Rx, Ry etc, or Ra, Rb... as well.

Ramie