What' s the difference between <= and := in VHDL

Question

Currently, I am learning some FPGA design techniques using VHDL, my problem is whether we can use := and <= interchangeably in VHDL or not, though I've seen the use of := in constants declarations and <= in assignments? Thanks in advance!

Ina

Answer 1

The rules are a little more complex than this, but basically: you use <= to do signal assignment, which takes effect on the next delta cycle. You use := to do variable assignment, which takes place immediately. So if you have a signal, you always use <=. If you have a variable, you always use :=.

Some places where this is not quite that case that you will commonly run into, for instance, initialization, where := is used even for signals.

So:

signal some_signal : std_logic := '0'; -- 0 initial value
...
variable some_variable : std_logic := '0'; -- 0 initial value
...
some_signal <= '1'; -- will assign 1 at the next time step (delta cycle)
...
some_variable := '1'; -- assigns 1 immediately

Antisocial

you mean I can use these two symbols interchangeably or there are some exceptions? @Antisocial – Ina

<= is for signals, := is for variables, except for initial values that both use := – Acker

For information on delta cycles, check out this good article on the subject: sigasi.com/content/vhdls-crown-jewel – Gingery

Answer 2

if you use signal temp:std_logic_vector then you'll have to use <=

if you use variable temp:std_logic_vector then you'll have to use :=

Zinkenite

Answer 3

<=

UseCase: Signal assignments that take place in the next cycle.

Example: signal temp:std_logic_vector

:=

UseCase: Variable assignments that take place immediately.

Example: variable temp:std_logic_vector

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Except for adding initial values to signals, you can also use :=.

Wrench