Verilog automatic task

Question

What does it mean if a task is declared with the automatic keyword in Verilog?

task automatic do_things;
  input [31:0] number_of_things;
  reg [31:0] tmp_thing;
  begin
    // ...
  end
endtask;

Note: This question is mostly because I'm curious if there are any hardware programmers on the site. :)

Vannavannatta

Answer 1

It means that the task is re-entrant - items declared within the task are dynamically allocated rather than shared between different invocations of the task.

You see - some of us do Verilog... (ugh)

Sailing

Answer 2

"automatic" does in fact mean "re-entrant". The term itself is stolen from software languages -- for example, C has the "auto" keyword for declaring variables as being allocated on the stack when the scope it's in is executed, and deallocated afterwards, so that multiple invocations of the same scope do not see persistent values of that variable. The reason you may not have heard of this keyword in C is that it is the default storage class for all types :-) The alternatives are "static", which means "allocate this variable statically (to a single global location in memory), and refer to this same memory location throughout the execution of the program, regardless of how many times the function is invoked", and "volatile", which means "this is a register elsewhere on my SoC or something on another device which I have no control over; compiler, please don't optimize reads to me away, even when you think you know my value from previous reads with no intermediate writes in the code".

"automatic" is intended for recursive functions, but also for running the same function in different threads of execution concurrently. For instance, if you "fork" off N different blocks (using Verilog's fork->join statement), and have them all call the same function at the same time, the same problems arise as a function calling itself recursively.

In many cases, your code will be just fine without declaring the task or function as "automatic", but it's good practice to put it in there unless you specifically need it to be otherwise.

Supraorbital

Answer 3

The "automatic" keyword also allows you to write recursive functions (since verilog 2001). I believe they should be synthesisable if they bottom out, but I'm not sure if they have tool support.

I too, do verilog!

Friulian

Answer 4

As Will and Marty say, the automatic was intended for recursive functions.

If a normal (i.e. not automatic) function is called with different values and processed by the simulator in the same time slice, the returned value is indeterminate. That can be quite a tricky bug to spot! This is only a simulation issue, when synthesised the logic will be correct.

Making the function automatic fixes this.

Lines

Answer 5

In computing, a computer program or subroutine is called re-entrant if multiple invocations can safely run concurrently (Wikipedia). In simple words, the keyword automatic makes it safe, when multiple instances of a task run at a same time. :D

Pneumatology

Answer 6

Automatic is just opposite to static in usual programming. So is the case with Verilog. Think of static variables, they cannot be re-initialized. See the Verilog description below:

for (int i = 0; i < 3; i++) begin
    static int f = 0;
    f = f + 1;
end

Result of the above program will be f = 3. Also, see the program below:

for (int i = 0; i < 3; i++) begin
    int f = 0;
    f = f + 1;
end

The result of above program is f = 1. What makes a difference is static keyword.

Conclusion is tasks in Verilog should be automatic because they are invoked (called) so many times. If they were static (if not declared explicitly, they are static), they could have used the result from the previous call which often we do not want.

Elaineelam