As I understand, when a CPU speculatively executes a piece of code, it "backs up" the register state before switching to the speculative branch, so that if the prediction turns out wrong ...

Is this correct that Hardware Lock Elision is disabled for all current CPUs due to Spectre mitigation, and any attempt to have a mutex using HLE intrinsics/instructions would result in usual mutex?...

Alright, so I know that if a particular conditional branch has a condition that takes time to compute (memory access, for instance), the CPU assumes a condition result and speculatively executes al...

CVE-2018-12126 has been assigned to MSBDS (Microarchitectural StoreBuffer Data Sampling), a vulnerability of Intel's processors belonging to the newly created MDS (Microarchitectural Data Sampling)...

The Memory Order Machine Clear performance event is described by the vTune documentation as: The memory ordering (MO) machine clear happens when a snoop request from another processor matches a ...

I was searching about hadoop and mapreduce with respect to straggler problems and the papers in this problem but yesterday I found that there is hadoop 2 with Yarn ,, unfortunately no paper is talk...

I'm trying to understand in detail what happens to instructions in the various stages of the skylake CPU pipeline when a branch is mis-predicted, and how quickly instructions from the correct branc...

I have read the wikipedia page about out-of-order execution and speculative exectution. What I fail to understant though are the similarities and differences. It seems to me that speculative exec...

CPU's use branch prediction to speed up code, but only if the first branch is actually taken. Why not simply take both branches? That is, assume both branches will be hit, cache both sides, and t...

What are the key differences between recently discovered hardware vulnerabilities Meltdown and Spectre? I know that they both rely on speculative execution, but how does they differ from each other...

I have a situation where some of the address space is sensitive in that you read it you crash as there is nobody there to respond to that address. pop {r3,pc} bx r0 0: e8bd8008 pop {r3, pc} 4: e...

Suppose I have pseudo C code like below: int x = 0; int y = 0; int __attribute__ ((noinline)) func1(void) { int prev = x; (1) x |= FLAG; (2) return prev; (3) } int main(void) { int tmp; ...

If I understand branching correctly (x86), the processor will sometimes speculatively take a code path and perform the instructions and 'cancel' the results of the wrong path. What if the operation...

In computer architecture, what is difference between (branch) prediction and speculation?? These seems very similar, but i think there is a subtle distinction between them.

I have a task which writes avro output in multiple directories organized by few fields of the input records. For example : Process records of countries across years and write in a directory str...

I'm trying to understand why we need all parts of the standard sample code: a `par` b `pseq` a+b Why won't the following be sufficient? a `par` b `par` a+b The above expression seems very des...

I have a reducer that needs to output results to different directories so that we can later use the output as input to Hive as a partitioned table. (Hive creates partitions based on folder name). I...

I am thinking about exploiting parallelism for one problem I am trying to solve. The problem is roughly this: given input (sequence of points) find a best output (biggest triangle composed from the...