I am new to PCI express, I want to read/write into PCI Express configuration space via MMIO addresses. I know how port mapped IO read/write into PCI express config space via 0xCFC and 0xCF8 port ad...

I have here Linux 4.4 (I used to work on an older kernel which failed in the same way) with a PCIe connected FPGA device and a driver for it which are both of my own design. These have been working...

Is it possible to issue a prefetch for an address backed by an MMIO region in a PCIe BAR (and mapped via either UC or WC page table entries)? I am currently issuing a load for this address which ca...

I know that the base address register (BAR) in PCI configuration space defines the start location of a PCI address, but how does the size of this region get established? Surely this is a property ...

Does QEMU emulate the PCIe Transaction Layer somehow? When I have a virtual Switch like (https://blogs.oracle.com/linux/post/a-study-of-the-linux-kernel-pci-subsystem-with-qemu) am I able to interc...

In the PCI Express Base specification, section 2.2.5 "First/Last DW Byte Enables Rules", it says a zero length read can be used as a flush request. However, in the linux kernel documentat...

I've tested CPU to GPU data transfer throughput with TensorFlow and it seems to be significantly lower than in PyTorch. For large tensors between 2x and 5x slower. In TF, I reach maximum speed for ...

Let's suppose a CPU wants to make a DMA read transfer from a PCI Express device. Communication to PCI Express devices is provided by transaction layer packets (TLP). Theoretically, the maximu...

If we look at a Haswell architectural diagram today we can see that there are PCIe lanes directly connected to the CPU (for graphics) as well as some of them routed to the the platform controller h...

After going through some basics documents what I understood is, Base Address Register is Address space which can be accessed by PCIe IP. PCIe IP can either transmit data in Base Address Register or...

I have an FPGA (Like most of the people asking this question) that gets configured after my Linux kernel does the initial PCIe bus scan and enumeration. As you can guess, the FPGA implements a PCIe...

I'm trying to understand how PCI segment(domain) is related to multiple Host Bridges? Some people say multiple PCI domains corresponds to multiple Host Bridges, but some say it means multip...

If I transfer a single byte from a CUDA kernel to PCI-E to the host (zero-copy memory), how much is it slow compared to transferring something like 200 Megabytes? What I would like to know, since ...

Hi I'm writing a kernel and plan to use MSI interrupt for PCI devices. However, I'm also quite confused by the documentations. My understanding about MSI are as follow: From PCI device point of ...

I understand that PCI and PCIe devices can be configured by the CPU (via code in the BIOS or OS) to respond to certain physical memory addresses by writing to specific areas of the device's configu...

In order to access PCI Configuration Space, I/O port address 0xCF8, 0xCFC is used according to various articles. mov eax, dword 0x80000000 mov dx, word 0x0CF8 out dx, eax mov dx, word 0x0CFC in e...

in a PCIe configuration, devices have dedicated addresses and they send data in Peer-to-Peer mode to each other - every device can write when it wills and the switches take care to correctly pass d...

In order to leverage the GPUs on a system, I'd like to be able to draw a block diagram and understand the connections represented by "nvidia-smi topo -m" output. Here is an example output: Can...

I want all read & write requests to a PCIe device to be cached by CPU caches. However, it does not work as I expected. These are my assumptions on write-back MMIO regions. Writes to the PCIe...

When writing data to a PCIe device, it is possible to use a write-combining mapping to hint the CPU that it should generate 64-byte TLPs towards the device. Is it possible to do something similar ...

After looking at the kernel docs here: https://www.kernel.org/doc/Documentation/PCI/pci.txt I am lost as to the ordering of function calls to set up and tear down a PCI driver. I have two question...

I have code, called from the probe() function of my PCIe driver (loosely based on this post): EDIT: Based on Andreas Bombe's response, I changed the code to use pci_iomap(), but I'm still experien...

I am currently working with the Xilinx XDMA driver (see here for source code: XDMA Source), and am attempting to get it to run (before you ask: I have contacted my technical support point of contac...

I have a PCIe device that will send a hardware interrupt when a data buffer is ready to be read. I believe the best approach for this is to use signals but I'm not entirely sure how. What I believe...

I am working with a high speed serial card for high rate data transfers from an external source to a Linux box with a PCIe card. The PCIe card came with some 3rd party drivers that use dma_alloc_co...