I'm using PCI-e port on Freescale MPC8308 processor (which is based on PowerPC architecture) and I have some problems when trying to use it. The endpoint PCI-e device has memory space equal to 256 ...

I am working on a network driver for an FPGA endpoint that supports multi-message MSI interrupts (not msix) on a PCIe bus. The host processor is an x86 Intel i7 620LM running on CentOS with a 4.2 k...

I found my MMIO read/write latency is unreasonably high. I hope someone could give me some suggestions. In the kernel space, I wrote a simple program to read a 4 byte value in a PCIe device's BAR0...

I am writing a PCIe driver for Linux, currently without DMA, and need to know how to read and write to the PCIe device once it is enabled from user space. In the driver I do the basics in probe()...

Can someone very briefly point out the differences between the memory bus and address bus in computer architectures ? Also when you say memory bus does it imply that you are referring to the databu...

Objective I'm trying to programmatically find out on which physical slot a particular PCIe device is connected. The premise is that I have the PCI-ID of a card that is surely occupying a slot, and...

What is DMA mapping and DMA engine in context of linux kernel? When DMA mapping API and DMA engine API can be used in Linux Device Driver? Any real Linux Device Driver example as a reference would ...

Can any body tell why MSI interrupts are not shareable in linux. PIN based interrupts can be shared by devices, but MSI interrupts are not shared by devices, each device gets its own MSI IRQ numbe...

I'm trying to get DMA transfer working between an FPGA and an x86_64 Linux machine. On the PC side I'm doing this initialization: //driver probe ... pci_set_master(dev); //set endpoint as master...

This book's PCI chapter explain about: int pci_enable_device(struct pci_dev *dev); however there's also: int pcim_enable_device (struct pci_dev * pdev); But besides stating it's a "Managed pc...

I am working on pcie based network driver. Different examples use one of pci_alloc_consistent or dma_alloc_coherent to get memory for transmission and reception descriptors. Which one is better if ...

I have a PCIe device with a userspace driver. I'm writing commands to the device through a BAR, the commands are latency sensitive and amount of data is small (~64-bytes) so I don't want to use DMA...

In CUDA programming guide it is stated that atomic operations on mapped pinned host memory "are not atomic from the point of view of the host or other devices." What I get from this sentence is tha...

I am trying to understand how PCI Express works so i can write a windows driver that can read and write to a custom PCI Express device with no on-board memory. I understand that the Base Address R...

Linux kernel 2.6 I've got an fpga that is loaded over GPIO connected to a development board running linux. The fpga will transmit and receive data over the pci-express bus. However, this is enumer...

As we know: http://en.wikipedia.org/wiki/IOMMU#Advantages Peripheral memory paging can be supported by an IOMMU. A peripheral using the PCI-SIG PCIe Address Translation Services (ATS) Page Requ...

I've been reading through the horror that is the PCIe spec, and still can't get any kind of resolution to the following question pair. Does PCIe allow for mapping huge (say 16GB) 64-bit non-prefe...

I heard about peer-to-peer memory transfers and read something about it but could not really understand how much fast this is compared to standard PCI-E bus transfers. I have a CUDA application wh...

I am trying to write a driver with custom mmap() function for PCIe BAR, with the goal to make this BAR cacheable in the processor cache. I am aware this is not the best way to achieve highest bandw...

I am working on a DMA routine to transfer data from PC to a FPGA on a PCIe card. I read DMA-API.txt and LDD3 ch. 15 for details. However, I could not figure out how to do a DMA transfer from PC to ...

I'm writing a linux device driver to allow an FPGA (currently connected to the PC via PCI express) to DMA data directly into CPU RAM. This needs to happen without any interaction and user space nee...

The data rate of cudaMemcpy operations is heavily influenced by the number of PCI-e 3.0 (or 2.0) lanes that are allocated to run from the CPU to GPU. I'm curious about how PCI-e lanes are used on N...