This is a very specific problem and I haven't heard back from the author, so I thought I would throw this out and see if my sanity is intact or not. This is in regard to this video regarding DMA on...

I am trying to implement UART in DMA mode to transmit a simple string every time a push button is pressed. So I have used CubeMX to generate the code and I have configured UART2 TX DMA in normal (...

I am working on a Linux module for IA64. My current problem is that the driver uses the PAGE_SIZE and PAGE_SHIFT macros for dma page allocation. The problem I am having is that the machine compilin...

Let's suppose a CPU wants to make a DMA read transfer from a PCI Express device. Communication to PCI Express devices is provided by transaction layer packets (TLP). Theoretically, the maximu...

I'm using an STM32H743. I have an external clock signal coming in on a GPIO pin, and I want to very accurately measure elapsed time between each rising (or falling) edge in the external clock signa...

Our task is intended to demonstrate the benefit of using DMA to copy a large amount of data versus relying on the processor to directly handle the copying. The processor is an STM32F407 on the ST d...

I know that for a network card, OS must allocate tx/rx rings for it so that when OS wants to receive/transmit packets, the network card will know where the packets are and which packets are to be t...

I'm using one STM32F4 and I want to communicate with my LSM303 accelerometer. For that I'm using I2C, and just using I2C works fine but when I try to use DMA with it, it stops working. When I use ...

Yes, I will ultimately be using this for DMA but lets leave coherency aside for the moment. I have 64 bit BAR registers, therefore, AFAIK, all of RAM (e.g. higher than 4G) is available for DMA. I a...

The following code is from include/asm-i386/io.h, and it is invoked from dma_map_single(). My understanding is that flush_write_buffers() is supposed to flush CPU memory cache before mapping the me...

in a PCIe configuration, devices have dedicated addresses and they send data in Peer-to-Peer mode to each other - every device can write when it wills and the switches take care to correctly pass d...

What is DMA and IOMMU ? How DMA and IOMMU used ? What if architecture does not support IOMMU ? How to use DMA without IOMMU ?

I'm trying to allocate a DMA buffer for a HPC workload. It requires 64GB of buffer space. In between computation, some data is offloaded to a PCIe card. Rather than copy data into a bunch of dinky ...

As mentioned above, what is the difference between a dma engine and a dma-controller (on focus on linux)? When does the linux dma engine come into place? Is this a special device or always part o...

Currently working on a PCI device driver. And the device is programmed like this: When a DMA transmission is done, the device send a MSI interrupt to PC with MSI data "001" binary. Now I'm writin...

Consider the diagrammed data cache architecture. (ASCII art follows.) -------------------------------------- | CPU core A | CPU core B | | |------------|------------| Devices | | Cache A1 | Ca...

I am using an stm32f40x microcontroller (UC), and I have to use its internal flash to store some data. The write operation, as you know, is very slow and occupies the UC for very long time. So I th...

I have configured a UART to receive in DMA mode where the size of the buffer is around 64 bytes. So, basically, the HAL_UART_RxCpltCallback() DMA receive complete interrupt will only fire when 64 c...

I have a project that I have used stm32f746g discovery board. It receives data with fixed size from Uart sequentially and to inform application about each data receive completed, dma callback is us...

I want to get data from a DMA enabled, PCIe hardware device into user-space as quickly as possible. Q: How do I combine "direct I/O to user-space with/and/via a DMA transfer" Reading through LDD...

I'm trying to understand everything that happens in between the time a packet reaches the NIC until the time the packet is received by the target application. Assumption: buffers are big enough to...

I am working with a high speed serial card for high rate data transfers from an external source to a Linux box with a PCIe card. The PCIe card came with some 3rd party drivers that use dma_alloc_co...

I am using a stm32f3 discovery board and the HAL from CubeMX. I am trying to use 2 ADC channels at ADC4. I configured DMA in circular mode. Befor the main loop in main, I call: HAL_ADC_Start_DMA(&...

Given the starting memory address & word count DMA controller transfers data while the CPU works on some other process. The Input Output processor too handles I/O processes given the starting a...

I'm a little bit confused about the cases in which CPU can direct transfer the data faster than DMA(Direct Memory Access Controller)? and vice-versa? Thanks