memory-fences Questions
5
Solved
What is meant by using an explicit memory fence?
Codfish asked 13/11, 2008 at 9:30
4
Solved
In Java 8 three memory barrier instructions were added to Unsafe class (source):
/**
* Ensures lack of reordering of loads before the fence
* with loads or stores after the fence.
*/
void loadFe...
Hernandez asked 12/5, 2014 at 7:28
4
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As known in since C++11 there are 6 memory orders, and in documentation written about std::memory_order_acquire:
http://en.cppreference.com/w/cpp/atomic/memory_order
memory_order_acquire
...
Oxy asked 30/7, 2016 at 18:13
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According to the Intel 64 and IA-32 Architectures Software Developer's Manual the LOCK Signal Prefix "ensures that the processor has exclusive use of any shared memory while the signal is asserted"...
Florescence asked 27/1, 2011 at 6:14
4
I am trying to understand what is a memory barrier exactly.
Based on what I know so far, a memory barrier (for example: mfence) is used to prevent the re-ordering of instructions from before to aft...
Edlyn asked 10/3, 2017 at 9:20
3
As we know from a previous answer to Does it make any sense instruction LFENCE in processors x86/x86_64? that we can not use SFENCE instead of MFENCE for Sequential Consistency.
An answer there su...
Comity asked 23/12, 2014 at 21:4
2
On x86, lock-prefixed instructions such as lock cmpxchg provide barrier semantics in addition to their atomic operation: for normal memory access on write-back memory regions, reads and writes are ...
Scherer asked 10/5, 2018 at 20:13
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The following Java code looks a little strange because I have simplified it down to the bare essentials. I think the code has an ordering problem. I am looking at the first table in the JSR-133 Coo...
Grapevine asked 12/2, 2018 at 19:27
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Preface
I recently came across some synchronization problems, which led me to spinlocks and atomic counters. Then I was searching a bit more, how these work and found std::memory_order and memory ...
Wilden asked 18/8, 2014 at 12:26
3
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I know that modern CPUs can execute out of order, However they always retire the results in-order, as described by wikipedia.
"Out of Oder processors fill these "slots" in time with other instruct...
They asked 8/9, 2011 at 10:52
3
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So I researched the topic for quite some time now, and I think I understand the most important concepts like the release and acquire memory fences.
However, I haven't found a satisfactory explanat...
Maddux asked 22/6, 2017 at 7:25
3
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If we have the following code in C#:
int a = 0;
int b = 0;
void A() // runs in thread A
{
a = 1;
Thread.MemoryBarrier();
Console.WriteLine(b);
}
void B() // runs in thread B
{
b = 1;
Thread...
Pacien asked 27/6, 2016 at 9:46
5
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Assuming that aligned pointer loads and stores are naturally atomic on the target platform, what is the difference between this:
// Case 1: Dumb pointer, manual fence
int* ptr;
// ...
std::atomic_...
Bernardina asked 5/1, 2013 at 1:58
1
Let's assume we have a memory area where some thread is writing data to. It then turns its attention elsewhere and allows arbitrary other threads to read the data. However, at some point in time, i...
Indispensable asked 1/7, 2016 at 13:26
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Unlike barrier() (which I think I understand), mem_fence() does not affect all items in the work group. The OpenCL spec says (section 6.11.10), for mem_fence():
Orders loads and stores of a work...
Neglect asked 6/10, 2011 at 12:3
4
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I've been experimenting with Electric Fence lately and I can't figure out how to use it with c++ code.
Here's an example:
// test.cpp
#include <cstdlib>
using namespace std;
int main() ...
Echo asked 29/2, 2012 at 7:8
1
Solved
According to the OpenMP Specification (v4.0), the following program contains a possible data race due to unsynchronized read/write of i:
int i{0}; // std::atomic<int> i{0};
void write() {
/...
Carabin asked 17/2, 2016 at 16:32
2
Solved
Java 8 has added three fences to sun.misc.Unsafe.
I feel confused after I read their documentation.
So, I searched the web, and found this link.
According to the page above, I believe these meth...
Boding asked 2/6, 2015 at 15:42
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When I run a block on any queue via dispatch_async or similar, does GCD provide thread fences around the block invocation? I would assume it does, but the documentation gives no hint one way or the...
Galan asked 25/4, 2015 at 12:12
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Am I wrong to assume that the atomic::load should also act as a memory barrier ensuring that all previous non-atomic writes will become visible by other threads?
To illustrate:
volatile bool arm1...
Mantellone asked 28/2, 2015 at 15:36
1
Ok, I have been reading the following Qs from SO regarding x86 CPU fences (LFENCE, SFENCE and MFENCE):
Does it make any sense instruction LFENCE in processors x86/x86_64?
What is the impact SFENC...
Maneater asked 22/12, 2014 at 1:40
2
Solved
The failure of Dekker-style synchronization is typically explained with reordering of instructions. I.e., if we write
atomic_int X;
atomic_int Y;
int r1, r2;
static void t1() {
X.store(1, std::m...
Lukelukens asked 2/12, 2014 at 11:57
3
Solved
Somewhere, one time I read about memory fences (barriers). It was said that memory fence causes cache synchronisation between several CPU cores.
So my questions are:
How does the OS (or CPU itse...
Elnora asked 13/9, 2014 at 9:43
3
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Can the compiler or processor reorder the following instructions so that another Thread sees a == 0 and b == 1?
Assuming int a = 0, b = 0; somewhere.
System.Threading.Interlocked.CompareExchange&...
Draftee asked 25/8, 2014 at 20:0
1
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Do the Linux glibc pthread functions on x86_64 act as fences for weakly-ordered memory accesses? (pthread_mutex_lock/unlock are the exact functions I'm interested in).
SSE2 provides some instructi...
Worden asked 15/6, 2014 at 20:45
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