memory-barriers Questions
3
A full/general memory barrier is one where all the LOAD and STORE operations specified before the barrier will appear to happen before all the LOAD and STORE operations specified after the barrier ...
Discomfit asked 25/8, 2014 at 1:47
1
Solved
Why does the LOCK prefix cause a full barrier on x86? (And thus it drains the store buffer and has sequential consistency)
For LOCK/read-modify-write operations, a full barrier shouldn't be requir...
Left asked 21/2, 2020 at 5:16
2
Solved
This question is a follow-up/clarification to this:
Does the MOV x86 instruction implement a C++11 memory_order_release atomic store?
This states the MOV assembly instruction is sufficient to per...
Insulin asked 20/2, 2020 at 6:40
4
Solved
I want to write portable code (Intel, ARM, PowerPC...) which solves a variant of a classic problem:
Initially: X=Y=0
Thread A:
X=1
if(!Y){ do something }
Thread B:
Y=1
if(!X){ do something }
...
Preemption asked 4/2, 2020 at 9:10
1
Solved
I am struggling with Section 5.1.2.4 of the C11 Standard, in particular the semantics of Release/Acquire. I note that https://preshing.com/20120913/acquire-and-release-semantics/ (amongst others) s...
Astrodynamics asked 9/2, 2020 at 16:0
4
Code within a single thread has certain memory guarantees, such as read after write (i.e. writing some value to a memory location, then reading it back should give the value you wrote).
What happe...
Inherited asked 5/2, 2020 at 17:53
1
Whilst trying to understand how SubmissionPublisher (source code in OpenJDK 10, Javadoc), a new class added to the Java SE in version 9, has been implemented, I stumbled across a few API calls to V...
Archerfish asked 7/2, 2020 at 18:30
1
C++ supported atomic thread fences, that is fences guaranteeing properties for thread that use std::atomic<> operations, with the function atomic_thread_fence. It takes a memory order paramet...
Banderole asked 13/12, 2019 at 4:44
2
Solved
Say, I have two threads A and B writing to a global Boolean variables fA and fB respectively which are initially set to false and are protected by std::mutex objects mA and mB respectively:
// Thr...
Metternich asked 25/1, 2017 at 9:12
3
Solved
I took the example about std::memory_order_seq_cst from:
http://en.cppreference.com/w/cpp/atomic/memory_order
#include <thread>
#include <atomic>
#include <cassert>
std::atomic&...
Malissamalissia asked 24/2, 2018 at 13:48
3
Solved
Suppose I have a thread A that writes to an atomic_int x = 0;, using x.store(1, std::memory_order_relaxed);. Without any other synchronization methods, how long would it take before other threads c...
Schwenk asked 3/5, 2017 at 2:15
3
Solved
cppreference.com provides this note about std::atomic_thread_fence (emphasis mine):
atomic_thread_fence imposes stronger synchronization constraints than an atomic store operation with the same ...
Outlay asked 12/7, 2018 at 22:12
4
Solved
I'm reading this article Memory Ordering at Compile Time from which said:
In fact, the majority of function calls act as compiler barriers,
whether they contain their own compiler barrier or no...
Insult asked 16/11, 2016 at 20:41
2
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Consider the following example taken from Wikipedia, slightly adapted, where the steps of the program correspond to individual processor instructions:
x = 0;
f = 0;
Thread #1:
while (f == 0);
p...
Petition asked 6/12, 2019 at 17:31
3
Solved
After seeing Herb Sutters excellent talk about "atomic weapons" I got a bit confused about the Relaxed Atomics examples.
I took with me that an atomic in the C++ Memory Model (SC-DRF = Sequentiall...
Proportionate asked 9/6, 2013 at 21:29
1
I'm not an ARM expert but won't those stores and loads be subjected to reordering at least on some ARM architectures?
atomic<int> atomic_var;
int nonAtomic_var;
int nonAtomic_var2;
voi...
Progressive asked 28/11, 2019 at 12:36
1
Solved
A lot of questions SO and articles/books such as https://mirrors.edge.kernel.org/pub/linux/kernel/people/paulmck/perfbook/perfbook.2018.12.08a.pdf, Preshing's articles such as https://preshing.com/...
Rasp asked 23/9, 2019 at 21:29
1
Solved
I've been reading about how the x86 memory model works and the significance of the barrier instructions on x86 and comparing to other architectures such as ARMv8. In both the x86 and ARMv8 architec...
Versicular asked 19/9, 2019 at 20:23
6
Solved
I have a question regarding the order of operations in the following code:
std::atomic<int> x;
std::atomic<int> y;
int r1;
int r2;
void thread1() {
y.exchange(1, std::memory_order_acq...
Adkins asked 2/10, 2018 at 10:27
1
Solved
Given an example:
#include <thread>
#include <iostream>
int main() {
int a = 0;
volatile int flag = 0;
std::thread t1([&]() {
while (flag != 1);
int b = a;
std::cout <&...
Marla asked 16/7, 2019 at 14:14
1
Solved
Vulkan spec states:
Write-after-read hazards can be solved with just an execution dependency, but read-after-write and write-after-write hazards need appropriate memory dependencies to be includ...
Brasilin asked 6/7, 2019 at 10:49
1
Solved
Let's say we have two thread. One that give a "go" and one that wait a go to produce something.
Is this code correct or can I have an "infinite loop" because of cache or something like that?
std...
Shriek asked 5/7, 2019 at 16:23
1
Solved
Let x and y be variables that are shared between main code and interrupt code.
My idea of volatile is that it is only and always needed for hardware variables and interrupt variables that are also...
Hauteur asked 27/6, 2019 at 12:49
3
I have a shared memory between multiple processes that interpets the memory in a certain way.
Ex:
DataBlock {
int counter;
double value1;
double ... }
What I want is for the counter to be updated/...
Crowell asked 6/1, 2012 at 14:35
1
Solved
I'm doing something about function safety. I need verify some X86 CPU instructions, such as LFENCE, SFENCE and MFENCE.
Now I can experience MFENCE according to Intel SDM chapter 8.2.3.4 "loads may...
Wicker asked 21/6, 2019 at 14:31
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