memory-barriers Questions
2
Solved
it make me confused, i reading golang memory model, https://golang.org/ref/mem
var l sync.Mutex
var a string
func f() {
a = "hello, world"
l.Unlock()
}
func main() {
l.Lock()
go f()...
Outrank asked 23/3, 2021 at 8:51
0
I would like to ask for some clarification about what discussed in this thread How is load->store reordering possible with in-order commit ? -- sorry I've not enough reputation to add comments d...
Auriferous asked 19/11, 2021 at 16:23
1
Solved
Consider this code:
std::atomic<int> x{ 0 };
std::atomic<int> y{ 0 };
int a;
int b;
void thread1()
{
//atomic op A
x.store(1, std::memory_order_relaxed);
//fence X
std::atomic_thr...
Sturdy asked 29/10, 2021 at 18:53
1
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I've been studying the memory model and saw this (quote from https://research.swtch.com/hwmm):
Litmus Test: Write Queue (also called Store Buffer)
Can this program see r1 = 0, r2 = 0?
// Thread 1 /...
Galactometer asked 9/9, 2021 at 3:51
1
With ARMv8.3 a new instruction has been introduced: LDAPR.
When there is a STLR followed by a LDAR to a different address, then these 2 can't be reordered and hence it is called RCsc (release consi...
Bully asked 6/8, 2021 at 5:44
7
Solved
A coworker and I write software for a variety of platforms running on x86, x64, Itanium, PowerPC, and other 10 year old server CPUs.
We just had a discussion about whether mutex functions such as ...
Cadaverous asked 26/7, 2011 at 23:10
2
I learnt from relaxed ordering as a signal that a store on an atomic variable should be visible to other thread in a "within a reasonnable amount of time".
That say, I am pretty sure it s...
Bettor asked 6/7, 2019 at 8:42
1
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With reference to the following code
auto x = std::atomic<std::uint64_t>{0};
auto y = std::atomic<std::uint64_t>{0};
// thread 1
x.store(1, std::memory_order_release);
auto one = y.loa...
Upland asked 25/5, 2021 at 18:28
1
I am studying the implementation of Seqlock. However all sources I found implement them differently.
Linux Kernel
Linux kernel implements it like this:
static inline unsigned __read_seqcount_beg...
Manda asked 2/6, 2019 at 23:30
2
Solved
According to https://en.cppreference.com/w/cpp/atomic/memory_order mutex.lock() and mutex.unlock() are acquire and release operations. An acquire operation makes it impossible to reorder later inst...
Mysterious asked 6/4, 2021 at 14:26
1
Do non-temporal stores (such as movnti), to the same cache line, issued by the same thread, reach the memory in program order?
So that for a system with NVRAM (like Intel Cascade Lake processor wit...
Hayfork asked 2/4, 2021 at 10:46
3
Solved
Can some of the load instructions be never globally visible due to store load forwarding ? To put it another way, if a load instruction gets its value from the store buffer, it never has to read fr...
Sweepings asked 30/5, 2018 at 16:56
1
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SFENCE prevents NT stores from committing from the store buffer ahead of SFENCE itself.
NT store data enters an LFB directly from the store buffer.
Therefore SFENCE can only guarantees the ordering...
Spermophyte asked 21/1, 2021 at 11:3
4
When implementing a class intended to be thread-safe, should I include a memory barrier at the end of its constructor, in order to ensure that any internal structures have completed being initializ...
Cullender asked 10/8, 2016 at 19:11
4
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Does Java allows output 1, 0? I've tested it very intensively and I cannot get that output. I get only 1, 1 or 0, 0 or 0, 1.
public class Main {
private int x;
private volatile int g;
// Execu...
Melburn asked 16/7, 2017 at 22:29
0
I'm learning memory barrier so I referred to memory-barriers documentation in linux kernel source code. And there is one description that I can't understand:
Control dependencies can be a bit tric...
Flouncing asked 26/9, 2020 at 7:4
3
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As I see from a test-case: https://godbolt.org/z/K477q1
The generated assembly load/store atomic relaxed is the same as the normal variable: ldr and str
So, is there any difference between relaxed ...
Ifill asked 9/9, 2020 at 11:5
1
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I was wondering about the equivalent of Java's "volatile", and found this answer.
An equivalent to Java volatile in Python
Which (basically) says that everything is effectively volatile i...
Elizabetelizabeth asked 24/7, 2020 at 17:42
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Recently I was reading the page The JSR-133 Cookbook for Compiler Writers by Doug Lea regarding JSR 133: JavaTM Memory Model and Thread Specification Revision.
There I read this line:
Memory barri...
Shocking asked 12/7, 2020 at 2:35
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Shared-memory multiprocessing systems typically need to generate a lot of traffic for cache coherence. Core A writes to cache. Core B might later read the same memory location. Therefore, core A, e...
Arlettaarlette asked 27/6, 2020 at 19:49
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x86 guarantees a total order over all stores due to its TSO memory model. My question is if anyone has an idea how this is actually implemented.
I have a good impression how all the 4 fences are im...
Denicedenie asked 19/6, 2020 at 7:31
2
Solved
https://en.cppreference.com/w/cpp/atomic/memory_order
From cppreference, memory_order_release can use until C++20? Can anyone explain why C++ Standard will delete this and which one memory_order w...
Durnan asked 10/5, 2020 at 15:28
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I want to use standalone memory barriers between atomic and non-atomic operations (I think it shouldn't matter at all anyway). I think I understand what a store barrier and a load barrier mean and ...
Parabasis asked 10/5, 2020 at 10:55
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TL;DR: In a producer-consumer queue does it ever make sense to put an unnecessary (from C++ memory model viewpoint) memory fence, or unnecessarily strong memory order to have better latency at the ...
Ember asked 4/5, 2020 at 11:33
4
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Say I have two threads that manipulate the global variable x. Each thread (or each core I suppose) will have a cached copy of x.
Now say that Thread A executes the following instructions:
set x t...
Bondon asked 12/3, 2017 at 11:23
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